Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.