Patents by Inventor Thomas Zou
Thomas Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11567885Abstract: The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.Type: GrantFiled: May 12, 2017Date of Patent: January 31, 2023Assignee: LG ELECTRONICS INC.Inventors: Milan Shah, Tariq Afzal, Thomas Zou
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Publication number: 20210271610Abstract: The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.Type: ApplicationFiled: May 12, 2017Publication date: September 2, 2021Applicant: LG ELECTRONICS INC.Inventors: Milan SHAH, Tariq AFZAL, Thomas ZOU
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Patent number: 10740261Abstract: A system and method for early data pipeline lookup in large cache design is provided. An embodiment of the disclosure includes searching one or more tag entries of a tag array for a tag portion of the memory access request and simultaneously with searching the tag array, searching a data work queue of a data array by comparing a set identifier portion of the memory access request with one or more data work queue entries stored in the data work queue, generating a pending work indicator indicating whether at least one data work queue entry exists in the data work queue that corresponds to the set identifier portion, and sending the memory access request to the data array or storing the memory access request in a side buffer associated with the tag array based on the pending work indicator and a search result of the tag array search.Type: GrantFiled: May 12, 2017Date of Patent: August 11, 2020Assignee: LG ELECTRONICS INC.Inventors: Arkadi Avrukin, Thomas Zou
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Patent number: 10705987Abstract: A control circuit for controlling memory prefetch requests to system level cache (SLC). The control circuit includes a circuit identifying memory access requests received at the system level cache (SLC), where each of the memory access requests includes an address (ANEXT) of memory to be accessed. Another circuit associates a tracker with each of the memory access streams. A further circuit performs tracking for the memory access streams by: when the status is tracking and the address (ANEXT) points to an interval between the current address (ACURR) and the last prefetched address (ALAST), issuing a prefetch request to the SLC; and when the status is tracking, and distance (ADIST) between the current address (ACURR) and the last prefetched address (ALAST) is greater than a specified maximum prefetch for the associated tracker, waiting for further requests to control a prefetch process.Type: GrantFiled: May 12, 2017Date of Patent: July 7, 2020Assignee: LG ELECTRONICS INC.Inventors: Arkadi Avrukin, Seungyoon Song, Tariq Afzal, Yongjae Hong, Michael Frank, Thomas Zou, Hoshik Kim, Jungsook Lee
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Patent number: 10515030Abstract: An Advanced Microcontroller Bus Architecture (AMBA)/Advanced eXtensible Interface (AXI) compatible device and corresponding method capable of efficient reordering of responses from a last level cache (LLC) and/or dynamic random access memory (DRAM).Type: GrantFiled: May 12, 2017Date of Patent: December 24, 2019Assignee: LG ELECTRONICS INC.Inventors: Arkadi Avrukin, Seungyoon Song, Milan Shah, Thomas Zou
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Publication number: 20190188164Abstract: An Advanced Microcontroller Bus Architecture (AMBA)/Advanced eXtensible Interface (AXI) compatible device and corresponding method capable of efficient reordering of responses from a last level cache (LLC) and/or dynamic random access memory (DRAM).Type: ApplicationFiled: May 12, 2017Publication date: June 20, 2019Applicant: LG ELECTRONICS INC.Inventors: Arkadi AVRUKIN, Seungyoon SONG, Milan SHAH, Thomas ZOU
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Publication number: 20190146922Abstract: A system and method for early data pipeline lookup in large cache design is provided. An embodiment of the disclosure includes searching one or more tag entries of a tag array for a tag portion of the memory access request and simultaneously with searching the tag array, searching a data work queue of a data array by comparing a set identifier portion of the memory access request with one or more data work queue entries stored in the data work queue, generating a pending work indicator indicating whether at least one data work queue entry exists in the data work queue that corresponds to the set identifier portion, and sending the memory access request to the data array or storing the memory access request in a side buffer associated with the tag array based on the pending work indicator and a search result of the tag array search.Type: ApplicationFiled: May 12, 2017Publication date: May 16, 2019Applicant: LG ELECTRONICS INC.Inventors: Arkadi AVRUKIN, Thomas ZOU
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Publication number: 20190138452Abstract: A control circuit for controlling memory prefetch requests to system level cache (SLC). The control circuit includes a circuit identifying memory access requests received at the system level cache (SLC), where each of the memory access requests includes an address (ANEXT) of memory to be accessed. Another circuit associates a tracker with each of the memory access streams. A further circuit performs tracking for the memory access streams by: when the status is tracking and the address (ANEXT) points to an interval between the current address (ACURR) and the last prefetched address (ALAST), issuing a prefetch request to the SLC; and when the status is tracking, and distance (ADIST) between the current address (ACURR) and the last prefetched address (ALAST) is greater than a specified maximum prefetch for the associated tracker, waiting for further requests to control a prefetch process.Type: ApplicationFiled: May 12, 2017Publication date: May 9, 2019Applicant: LG ELECTRONICS INC.Inventors: Arkadi AVRUKIN, Seungyoon SONG, Tariq AFZAL, Yongjae HONG, Michael FRANK, Thomas ZOU, Hoshik KIM, Jungsook LEE
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Patent number: 9384156Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.Type: GrantFiled: November 21, 2013Date of Patent: July 5, 2016Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Nhon Quach, Stephen Z. Au, Thomas Zou, Tracy Sharpe
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Publication number: 20150143014Abstract: One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.Type: ApplicationFiled: November 21, 2013Publication date: May 21, 2015Applicant: Microsoft CorporationInventors: Nhon Quach, Stephen Z. Au, Thomas Zou, Tracy Sharpe