Abstract: A semiconductor memory testing implementation suitable for build-in self repair (BISR) memories provides, in one embodiment, a memory testing circuit configuration including an output register for receiving digital data. A plurality of shift registers serially output the digital data to be received by the output register. Each one of the plurality of shift registers includes a feedback path for enabling the digital data output by a corresponding one of the plurality of shift registers to be input back into the corresponding shift register in a same sequence as the digital data is output from the corresponding shift register.

Abstract: A multiport BIST method and apparatus therefor are disclosed. The multiport BIST is advantageously based on adapting a single port BIST method by dividing the memory into sections based on the number of ports and applying the single port BIST simultaneously through all ports simultaneously (inverting where appropriate), so as to test the sections in parallel. In one embodiment of the invention, an integrated circuit device comprises a multiport memory and a built-in self-test (BIST) unit that applies a first test pattern of read and write operations to a first port of the memory and applies a second test pattern of read and write operations to a second port of the memory. The addresses in the first test pattern are offset from addresses in the second test pattern by a fixed amount. The ports preferably have adjacent bit lines, and the data values conveyed by the first and second test patterns are preferably complementary.

Abstract: A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Abstract: An integrated circuit device is disclosed having a boundary scan chain and a hardwired BIST unit that is configurable via the control circuitry for the boundary scan chain. In one embodiment, the device includes application logic, a BIST unit, a boundary scan chain, a register, and a test access port. The application logic is the logic that provides the intended function of the chip. The BIST unit is configured to apply test patterns to the application logic to verify its functionality. The boundary scan chain is configured to sample input signals to the application logic and to control output signals from the application logic. The register stores an operational mode parameter for the BIST. The test access port provides external access to the boundary scan chain and the register, and is configured to control a clock signal to the BIST unit in accordance with the BIST operational mode parameter.