Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

Abstract: A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

Abstract: A communication switch having heterogeneous ports. The heterogeneous ports are connected to nodes which may be operating at different frequencies and which may have different optical characteristics. In addition to the ports, the switch of the present invention includes a matrix controller and a matrix switch which is connected to the ports. When two ports want to communicate, the matrix controller commands the matrix switch to establish a physical connection between the ports. According to the present invention, data is transferred between the ports via the matrix switch in a serial and asynchronous manner. Because data is serially and asynchronously transmitted, high data rates through the matrix switch may be achieved.

Abstract: A partitioned switch having distributed clocks includes a global matrix switch and one or more self-contained mini-switches. The mini-switches each contain ports connected via a local matrix switch. Communication between ports located in the same mini-switch is performed synchronously and in parallel via the local matrix switch. Communication between ports located in different mini-switches is performed asynchronously and serially via the global matrix switch. The mini-switches control the global matrix switch by serially and asynchronously sending control information to the global matrix switch.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

Abstract: An electro-optical transducer assembly for translating between an optical high speed serial data transmission path and parallel electrical data transmission paths is provided by a light emitting or light detecting device with serial terminals, a logic chip with timing, amplifying, serializing or de-serializing circuitry, and a multi-layer coupling chip with parallel input or output contacts mounted between the device and the logic chip for coupling the serial terminals of the device to the serial terminals on the logic chip and coupling the logic chip parallel terminals to the parallel input or output contacts.

Abstract: A high content LCD includes, a glass plate; a polysilicon deposited substrate supporting a matrix of electrodes; each of the electrodes defining a picture element (pel) in the LCD; a liquid crystal material interposed between the glass plate and the substrate; a plurality of FET devices, there being one or more FET device associated with each of the electrodes; and means for selectively actuating the FET devices to display an image on the LCD.

Abstract: An electrochromic matrix display of the kind in which the display electrodes are supported on a substrate above a corresponding matrix of transistor switches employs constant current writing and potentiostatic erasure. The transistors are switchable by signals applied on respective gate lines to pass electric current on the respective drive lines to their display electrodes. Gate and drive selection means define the active gate and drive lines During erasure, the potentiostatic erase voltage is applied to both ends of the selected drive lines simultaneously to speed up the current limited asynchronous erase operation. Optionally, the display may be driven alternately from opposite ends of the drive lines during a line-by-line writing operation.