Abstract: The optimized-delay multiplexer includes at least two pass elements that are respectively driven via a first path by a control signal directly, and via a second path by the control signal inverted by an inverter. A further pass element is connected in the first path to simulate the delay caused by the inverter. As a result, the at least two pass elements are switched simultaneously.

Abstract: An integrated dynamic semiconductor memory has memory cells which are provided in a matrix-like memory cell array and are combined to form units with column lines and row lines. The integrated dynamic semiconductor memory has a decoder for selecting one of the column lines and a sense amplifier which is jointly allocated to all the memory cells in a selected column line. The sense amplifier is connected to a data signal line for the purpose of further processing a data signal from an addressed memory cell. The decoder for selecting one of the column lines and the sense amplifier are provided at the edge and on opposite sides of the memory cell array. By separating the control for selection of the column lines and of the data output path, successive steps in the process of read access can be controlled in a self-adjusting manner by the respective preceding signal.

Abstract: A semiconductor memory of the dynamic random access type (DRAM) includes memory cells combined in addressable units of bit lines and word lines. Each memory cell array is allocated a row decoder for selection of one of the word lines and a column decoder for selection of one of the bit lines, in the memory cell array. The row decoder is connected to a row selection signal line for transmission of a selection signal. The row decoder is disposed at an edge of the memory cell array allocated thereto, and between the memory cell arrays. The column decoder is connected to the row selection signal line. The column decoder is disposed on the outer edge area both of the memory cell array allocated thereto and of the memory field. A method for actuating a memory cell in such a semiconductor memory is also provided.

Abstract: An electronic circuit configuration having two lines and a detector device which is allocated to the two lines. The circuit configuration detects a potential difference on the lines and controls a change in the line potentials in response to this. Each line is allocated a switch that is driven by the detector device and, after actuation by the detector device, connects the potential of an associated line to a reference-ground potential that is coupled to the switch.

Abstract: The integrated circuit has two inputs each supplying one input clock. Two outputs each output one output clock. The first logic levels of the output clock signals at the outputs do not overlap in time.

Abstract: An integrated dynamic semiconductor memory has memory cells which are provided in a matrix-like memory cell array and are combined to form units with column lines and row lines. The integrated dynamic semiconductor memory has a decoder for selecting one of the column lines and a sense amplifier which is jointly allocated to all the memory cells in a selected column line. The sense amplifier is connected to a data signal line for the purpose of further processing a data signal from an addressed memory cell. The decoder for selecting one of the column lines and the sense amplifier are provided at the edge and on opposite sides of the memory cell array. By separating the control for selection of the column lines and of the data output path, successive steps in the process of read access can be controlled in a self-adjusting manner by the respective preceding signal.

Abstract: The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Abstract: A dynamic memory includes memory cells combined to form blocks and blocks combined to form at least one block group. The memory also includes bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells within the blocks, at least one redundant word line in at least one of the blocks, and a decoder unit connected to the word lines. The redundant word lines are connected to the redundant memory cells for selecting the redundant memory cells. A redundant word line, after redundancy programming has been carried out, selectively replaces a word line in any of the blocks. In a first mode of operation, no more than one of the word lines is selected simultaneously per block group. In a second mode of operation, more than one of the word lines is selected simultaneously per block group, and redundancy programming is deactivated.

Abstract: A databus includes n+1 (n.gtoreq.2) lines which form n true-only lines and lead from n input blocks to n output blocks. One of the true-only lines as well as a monitoring line are associated with one of the input blocks which is located at a start of the databus and has the longest signal delay time. A NAND gate is connected downstream of the input block at the start of the databus and has an output connected to each output block.