Patents by Inventor Thorbjorn Ebefors

Thorbjorn Ebefors has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210162457
    Abstract: There is provided systems, devices and methods for system (100) for generating an acoustic-potential field of ultrasonic waves, using an array of acoustic micromachined ultrasonic transducer, MUT, elements, the array of acoustic MUT elements being comprised in one or more micromachined ultrasonic transducer, MUT; and having a controller being communicably connected to two or more of said acoustic MUT elements in said array, and being configured to control each of the two or more acoustic MUT elements to emit a modulated ultrasonic signal comprising a plurality of ultrasound waves towards one or more common focal points according to a respective phase shift of each of the two or more acoustic MUT elements, configured to cause the ultrasound waves of the modulated ultrasonic signals to be constructively combined at the common focal point(s), so as to generate an acoustic-potential field of ultrasonic waves.
    Type: Application
    Filed: April 26, 2019
    Publication date: June 3, 2021
    Inventor: Thorbjörn EBEFORS
  • Patent number: 9936918
    Abstract: A method of providing a metal coating on a substrate (10), and electrically insulating sections/parts of the metal coated substrate from each other. A substrate is provided with an insulating material in the substrate, the insulating first material extending through the thickness of the substrate and protruding above one surface of the substrate. It forms an enclosed section/portion (14) of the substrate. A protective structure (15) is provided on the insulating material such that it covers the entire circumference thereof. The insulating material is selectively etched to create an under-etch (18) under the protective structure. Finally conductive material (19) is deposited to provide a metal coating over the substrate, whereby the under-etch will provide a disruption in the deposited metal coating, thereby electrically insulating the enclosed section from the surrounding substrate.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 10, 2018
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Edvard Kalvesten, Thorbjorn Ebefors, Anders Eriksson
  • Patent number: 9718674
    Abstract: A device includes a base substrate (700) with a micro component (702) attached thereto. Suitably it is provided with routing elements (704) for conducting signals to and from the component (702). It also includes spacer members (706) which also can act as conducting structures for routing signals vertically. There is a capping structure (708) of a glass material, provided above the base substrate (700), bonded via the spacer members (706), preferably by eutectic bonding, wherein the capping structure (708) includes vias (710) including metal for providing electrical connection through the capping structure. The vias can be made by a stamping/pressing method entailing pressing needles under heating to soften the glass and applying pressure, to a predetermined depth in the glass. However, other methods are possible, e-g- drilling, etching, blasting.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 1, 2017
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Edvard Kalvesten, Thorbjorn Ebefors, Niklas Svedin
  • Patent number: 9620390
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 11, 2017
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edvard Kalvesten, Tomas Bauer
  • Patent number: 9613863
    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 ?m are provided on both sides of the wafer.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 4, 2017
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Henrik Knutsson
  • Patent number: 9511999
    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 6, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Niklas Svedin
  • Patent number: 9514985
    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 ?m are provided on both sides of the wafer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 6, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Henrik Knutsson
  • Patent number: 9484293
    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 1, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjörn Ebefors, Daniel Perttu
  • Patent number: 9448401
    Abstract: A layered micro-electronic and/or micro-mechanic structure comprises at least three alternating electrically conductive layers with insulating layers between the conductive layers. There is also provided a via in a first outer layer, said via comprising an insulated conductive connection made of wafer native material through the layer, an electrically conductive plug extending through the other layers and into said via in the first outer layer in order to provide conductivity through the layers, and an insulating enclosure surrounding said conductive plug in at least one selected layer of said other layers for insulating said plug from the material in said selected layer. It also relates to micro-electronic and/or micro-mechanic device comprising a movable member provided above a cavity such that it is movable in at least one direction. The device has a layered structure according to the invention. Methods of making such a layered MEMS structure is also provided.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 20, 2016
    Assignee: Silex Microsystems AB
    Inventors: Thorbjorn Ebefors, Edvard Kalvesten, Peter Agren, Niklas Svedin
  • Publication number: 20160207758
    Abstract: A device includes a base substrate (700) with a micro component (702) attached thereto. Suitably it is provided with routing elements (704) for conducting signals to and from the component (702). It also includes spacer members (706) which also can act as conducting structures for routing signals vertically. There is a capping structure (708) of a glass material, provided above the base substrate (700), bonded via the spacer members (706), preferably by eutectic bonding, wherein the capping structure (708) includes vias (710) including metal for providing electrical connection through the capping structure. The vias can be made by a stamping/pressing method entailing pressing needles under heating to soften the glass and applying pressure, to a predetermined depth in the glass. However, other methods are possible, e-g- drilling, etching, blasting.
    Type: Application
    Filed: August 26, 2014
    Publication date: July 21, 2016
    Inventors: Edvard KALVESTEN, Thorbjorn EBEFORS, Niklas SVEDIN
  • Publication number: 20160172241
    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings<10 ?m are provided on both sides of the wafer.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 16, 2016
    Inventors: Thorbjorn EBEFORS, Henrik KNUTSSON
  • Patent number: 9362139
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: June 7, 2016
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Tomas Bauer
  • Patent number: 9355895
    Abstract: A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in the recesses and holes; metallizing the holes and recesses; and removing the oxide layer in the bottom of the holes to provide contact between the back side and the front side of the wafer. A semiconductor device, including a substrate having at least one metallized via extending through the substrate and at least one metallized recess forming a routing together with the via. There is an oxide layer on the front side field and on the back side field. The metal in the recess and the via is flush with the oxide on the field on at least the front side, whereby a flat front side is provided. The thickness of the semiconductor device is <300 ?m.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: May 31, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Daniel Perttu
  • Patent number: 9312217
    Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: April 12, 2016
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Tomas Bauer, Thorbjörn Ebefors
  • Publication number: 20160035662
    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Inventors: Thorbjörn EBEFORS, Daniel PERTTU
  • Patent number: 9240373
    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 19, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjörn Ebefors, Daniel Perttu
  • Patent number: 9224681
    Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 29, 2015
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Daniel Perttu
  • Patent number: 9190356
    Abstract: The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 17, 2015
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjörn Ebefors, Daniel Perttu
  • Publication number: 20150255344
    Abstract: A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The the poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectiveley deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings<10 ?m are provided on both sides of the wafer.
    Type: Application
    Filed: September 27, 2013
    Publication date: September 10, 2015
    Inventors: Thorbjorn Ebefors, Henrik Knutsson
  • Publication number: 20150076677
    Abstract: The present interposer makes it possible to tailor the coefficient of thermal expansion of the interposer to match components to be attached thereto within very wide ranges. The semiconductor interposer, includes a substrate of a semiconductor material having a first side and an opposite second side. There is at least one conductive wafer-through via including metal. At least one recess is provided in the first side of the substrate and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure. The exposed surfaces of the metal-filled via and metal-filled recess are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via includes a narrow part and a wider part, and contact elements are provided on the routing structure having an aspect ratio, height:diameter, <1:1, preferably 1:1 to 2:1.
    Type: Application
    Filed: April 15, 2013
    Publication date: March 19, 2015
    Applicant: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Daniel Perttu