Abstract: A power semiconductor device includes a back side emitter region laterally segmented into at least first and second emitter regions. The first emitter region has a first lateral total area (A1) and, with respect to the first lateral total area and a second conductivity type, a medium dopant dose (D_M). The second emitter region has a second lateral total area (A2) and includes one or more first subregions and one or more second subregions, where A1<0.5*A2. The first subregion(s) form/forms a first portion of the second lateral total area and has/have, with respect to the first portion and the second conductivity type, a high dopant dose (D_H). The second subregion(s) form/forms a second portion of the second lateral total area and has/have, with respect to the second portion and the second conductivity type, a low dopant dose (D_L), where D_H>1.5*D_M and D_L<0.5*D_M.

Abstract: In a power semiconductor device, a deep semiconductor region is provided in addition to a barrier structure. The barrier structure is spatially separated from a trench structure in an active region and arranged in a transition region between the active region and an edge termination region of the power semiconductor device.

Abstract: A semiconductor device includes trenches extending into a semiconductor substrate from a first surface and patterning the substrate into mesas, including first and second mesas. Each of the first and second mesas includes a first portion of a first conductivity type and a second portion of a second conductivity type. The first portion is arranged between the first surface and the second portion. The first portion of each of the first and second mesas is electrically connected by a contact structure at the first surface. A source region of the second conductivity type included in the first mesa and omitted in the second mesa is electrically connected to the contact structure. At a vertical reference level in the second portion of the first mesa, a doping concentration is by at least a factor of ten higher than at the vertical reference level in the second portion of the second mesa.

Abstract: A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type and load terminals at opposite first and second sides of the semiconductor body. The power semiconductor device is configured to conduct a forward load current between the load terminals. A trench grid structure extending from the first side into the semiconductor body includes a plurality of macro cells. Each macro cell includes at least one first type micro cell configured for the forward load current conduction and a number of second type micro cells not configured for the forward load current conduction. Each micro cell is laterally confined by a respective portion of the trench grid structure. In each macro cell, the number of the second type micro cells is equal to or greater than the number of first type micro cells.

Abstract: A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.

Abstract: The invention relates to a slicing apparatus for slicing food products, in particular to a high-performance slicer, comprising a product feed that feeds products to be sliced on one or more tracks in a feed direction to a cutting region in which the products are cut into slices during a cutting operation of the slicing apparatus by means of a cutting blade, in particular a revolving and/or rotating cutting blade, that performs cutting movements; a portioning region in which portions are formed from the slices and each comprise one slice or a plurality of slices disposed at least partly above one another; and a control device that controls the cutting operation and that has operating information that relates to the cutting operation, wherein a treatment agent device for providing a liquid treatment agent is integrated into the slicing apparatus and is configured to provide the treatment agent during the cutting operation such that the treatment agent is applied to a respective cut surface of a product and/or t

Abstract: A power semiconductor device and a method of producing a power semiconductor device are presented. The power semiconductor device is, for example, embodied as an IGBT and includes a deep cross trench which extends below trenches that include, e.g., control and source trench electrodes.

Abstract: A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions.

Abstract: A power semiconductor device includes an active region with power cells, each configured to conduct a load current portion between first and second load terminals. Each power cell includes: trenches and mesas laterally confined by the trenches and in a vertical direction adjoining a drift region. The mesas include an active mesa having a source region of a first conductivity type and a body region of a second conductivity type separating the source region from the drift region. Both the source and body region are electrically connected to the first load terminal. At least one trench adjacent to the active mesa is configured to induce a conductive channel in the active mesa. A punch through structure s electrically separated from the active mesa by at least one separation stack.

Abstract: The invention relates to a slicing apparatus for slicing food products, in particular to a high-performance slicer, comprising a product feed that feeds products to be sliced on one or more tracks in a feed direction to a cutting region in which the products are cut into slices during a cutting operation of the slicing apparatus by means of a cutting blade, in particular a revolving and/or rotating cutting blade, that performs cutting movements; a portioning region in which portions are formed from the slices and each comprise one slice or a plurality of slices disposed at least partly above one another; and a control device that controls the cutting operation and that has operating information that relates to the cutting operation, wherein a treatment agent device for providing a liquid treatment agent is integrated into the slicing apparatus and is configured to provide the treatment agent during the cutting operation such that the treatment agent is applied to a respective cut surface of a product and/or t

Abstract: A power semiconductor device first trench structures extending from a first main surface into a semiconductor body up to a first depth. The first trench structures extend in parallel along a first lateral direction. Each first trench structure includes a first dielectric and a first electrode. The power semiconductor device further includes second trench structures extending from the first main surface into the semiconductor body up to a second depth that is smaller than the first depth. The second trench structures extend in parallel along a second lateral direction and intersect the first trenches at intersection positions. Each second trench structure includes a second dielectric and a second electrode. The second dielectric is arranged between the first electrode and the second electrode at the intersection positions.