Abstract: A processing chamber and method of etching a semiconductor substrate are presented. The processing chamber is symmetric, with the centerlines of a chuck and stem of a stage to retain a semiconductor substrate aligned with a centerline of a passage in a core of a pump used to evacuate the processing chamber and with a centerline of a gas port through which gas is introduced to the processing chamber. The stem extends through the passage and a spiral groove is formed in the passage in only one of the stem or an inner surface of the core to provide pumping action to counter back streaming of the gas from an exhaust of the pump in an intermediate and viscous flow regime inside a gap between the stem and the core.

Abstract: A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.

Abstract: A processing chamber and method of etching a semi-conductor substrate are presented. The processing chamber is symmetric, with the centerlines of a chuck and stem of a stage to retain a semi-conductor substrate aligned with a centerline of a passage in a core of a pump used to evacuate the processing chamber and with a center-line of a gas port through which gas is introduced to the processing chamber. The stem extends through the passage and a spiral groove is formed in the passage in only one of the stem or an inner surface of the core to provide pumping action to counter back streaming of the gas from an exhaust of the pump in an intermediate and viscous flow regime inside a gap between the stem and the core.

Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.

Abstract: A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

Abstract: Etch in a thermal etch reaction is predicted using a machine learning model. Chemical characteristics of an etch process and associated energies in one or more reaction pathways of a given thermal etch reaction are identified using a quantum mechanical simulation. Labels indicative of etch characteristics may be associated with the chemical characteristics and associated energies of the given thermal etch reaction. The machine learning model can be trained using chemical characteristics and associated energies as independent variables and labels as dependent variables across many different etch reactions of different types. When chemical characteristics and associated energies for a new thermal etch reaction are provided as inputs in the machine learning model, the machine learning model can accurately predict etch characteristics of the new thermal etch reaction as outputs.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Abstract: A processing chamber and method of etching a semi-conductor substrate are presented. The processing chamber is symmetric, with the centerlines of a chuck and stem of a stage to retain a semi-conductor substrate aligned with a centerline of a passage in a core of a pump used to evacuate the processing chamber and with a center-line of a gas port through which gas is introduced to the processing chamber. The stem extends through the passage and a spiral groove is formed in the passage in only one of the stem or an inner surface of the core to provide pumping action to counter back streaming of the gas from an exhaust of the pump in an intermediate and viscous flow regime inside a gap between the stem and the core.

Abstract: A high density, controlled integrated circuits factory having process modules occupying approximately two-thirds of the factory floor space with the remaining one-third of the factory floor space being used for servicing the process modules and for loading and unloading wafers to and from the process modules. A subfloor is provided below the factory floor to allow service lifts to travel across the factory. Service lifts can be raised to the factory floor level to service process modules. Overhead lines are also provided over the process modules to transport service items as well as wafers across the factory.

Abstract: High aspect ratio features are etched using a plasma etching apparatus that can alternate between accelerating negative ions of reactive species at a low energy and accelerating positive ions of inert gas species at a high energy. The plasma etching apparatus can be divided into at least two regions that separate a plasma-generating space from an ionization space. Negative ions of the reactive species can be generated by electron attachment ionization in the ionization space when a plasma is ignited in the plasma-generating space. Positive ions of the inert gas species can be generated by Penning ionization in the ionization space when the plasma is quenched in the plasma-generating space.

Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.

Abstract: The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate.

Abstract: A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.

Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.