Abstract: A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.

Abstract: A down-converter converts an amplitude modulated high frequency signal into a low frequency or baseband signal. A first mixer (30, 32) mixes the high frequency signal into a composite signal having an in-phase component and a quadrature component. A complex bandpass filter (34) bandwidth limits the composite signal into a bandwidth limited signal with an in-phase component and a quadrature component. A second mixer (36, 38) mixes the bandwidth limited signal into an intermediate signal with an in-phase component and a quadrature component, and an adder (40) adds one component of the intermediate signal to the other. A similar up-converter performs the reverse process.

Abstract: A base station in a radio telecommunication system, transforms real digital wideband high-frequency signals into a set of complex digital baseband signals and vice versa. The base station receives a set of complex digital baseband signals having an “I” and a “Q” components. A portion of these signals are modulated and then converted into complex digital high-frequency signals. The complex digital high-frequency signals are then filtered via bilinear digital ladder bandpass filters to retrieve real digital narrowband high-frequency signals. The outputs of these filters are the same corresponding “I” and “Q” components at the narrowband frequencies. These signals are further combined to form real digital wideband high-frequency signals. Finally, the combined signals are converted through a D/A converter to real analog wideband high-frequency bandpass signals.

Abstract: A digital and a multiplication method are described, which lead to an efficient architecture for hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.

Abstract: A base station in a radio communication system uses complex bandpass filters &OHgr;1, &OHgr;2, . . . , &OHgr;N and down-sampling to channelize a wideband signal containing many channels or channel groups.

Abstract: A base station in a radio communication system uses complex bandpass filters &OHgr;1, &OHgr;2, . . . ,&OHgr;N and down-sampling to channelize a wideband signal containing many channels or channel groups.

Abstract: A desired programmable complex analog bandpass filter is replaced by a "black box" that receives an analog continuous-time signal and delivers an analog continuous-time signal, just as the analog filter would, but internally realizes the programmability with a programmable discrete-time system. The transfer function of the "black box" is the same as the transfer function of the analog filter. The "black box" includes an anti-aliasing filter, an A/D-converter, a complex digital bandpass filter (16), a D/A-converter (18) and an anti-imaging filter (20).