Patents by Inventor Thoru Nojiri

Thoru Nojiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RISC system capable of performing calls and returns without advancing or restoring window pointers
    Patent number: 5450610
    Abstract: In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating the main memory is provided in the same instruction.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: September 12, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Tan Watanabe, Keiichi Kurakazu, Yugo Kashiwagi, Keisuke Toyama, Thoru Nojiri
  • RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled
    Patent number: 5214786
    Abstract: In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.Besides, an address part for designating the main memory is provided in the same instruction.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: May 25, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tan Watanabe, Keiichi Kurakazu, Yugo Kashiwagi, Keisuke Toyama, Thoru Nojiri