Patents by Inventor Thow Pang Chong
Thow Pang Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8739099Abstract: A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.Type: GrantFiled: July 20, 2008Date of Patent: May 27, 2014Assignee: Altera CorporationInventors: Victor R. Maruri, Boon Jin Ang, Henry Y. Lui, Surinder Singh, Thow Pang Chong, Tony K. Ngai
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Patent number: 8694944Abstract: Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.Type: GrantFiled: December 21, 2009Date of Patent: April 8, 2014Assignee: Altera CorporationInventors: Sze Huey Soo, Thow Pang Chong, Boon Jin Ang, Kar Keng Chua
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Patent number: 8659334Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: July 6, 2012Date of Patent: February 25, 2014Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Publication number: 20120274375Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: ApplicationFiled: July 6, 2012Publication date: November 1, 2012Inventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Patent number: 8232823Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.Type: GrantFiled: June 5, 2009Date of Patent: July 31, 2012Assignee: Altera CorporationInventors: Teik Wah Lim, Eng Huat Lee, Ie Chen Chia, Thow Pang Chong, Boon Jin Ang, Kim Pin Tan
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Patent number: 8151224Abstract: A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices.Type: GrantFiled: December 29, 2008Date of Patent: April 3, 2012Assignee: Altera CorporationInventors: Boon Jin Ang, Kar Keng Chua, Choong Kit Wong, Kok Yoong Foo, Thow Pang Chong
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Patent number: 8037377Abstract: A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.Type: GrantFiled: May 27, 2008Date of Patent: October 11, 2011Assignee: Altera CorporationInventors: Ie Chen Chia, Eng Huat Lee, Thow Pang Chong, Boon Jin Ang, Kar Keng Chua
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Patent number: 8037444Abstract: An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.Type: GrantFiled: July 20, 2006Date of Patent: October 11, 2011Assignee: Altera CorporationInventors: Boon Jin Ang, Bee Yee Ng, Thow Pang Chong, Yu Fong Tan
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Patent number: 7843216Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.Type: GrantFiled: August 18, 2008Date of Patent: November 30, 2010Assignee: Altera CorporationInventors: Darren van Wageningen, Curt Wortman, Boon-Jin Ang, Thow-Pang Chong, Dan Mansur, Ali Burney
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Patent number: 7683689Abstract: A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.Type: GrantFiled: April 10, 2008Date of Patent: March 23, 2010Assignee: Altera CorporationInventors: Tat Mun Lui, Kar Keng Chua, Boon Jin Ang, Thow Pang Chong, Kam Fai Suit
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Patent number: 7639047Abstract: A circuit includes a clock routing network. The clock routing network includes first and second clock paths. The first clock path routes a first clock signal to sub-circuits in the circuit. The first clock path has first buffers that buffer the first clock signal at the sub-circuits and first conductors in a first conductive layer of the circuit that transmit the first clock signal. The second clock path routes a second clock signal to the sub-circuits. The second clock path has second buffers that buffer the second clock signal at the sub-circuits, second conductors in the first conductive layer that transmit the second clock signal, and third conductors in a second conductive layer of the circuit. The second clock signal is routed through the third conductors at overlaps between the first clock path and the second clock path.Type: GrantFiled: March 22, 2008Date of Patent: December 29, 2009Assignee: Altera CorporationInventors: Boon Jin Ang, Bee Yee Ng, Eng Huat Lee, Thow Pang Chong, Teng Kuan Koay
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Publication number: 20080297192Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.Type: ApplicationFiled: August 18, 2008Publication date: December 4, 2008Applicant: ALTERA CORPORATIONInventors: Darren van WAGENINGEN, Curt WORTMAN, Boon-Jin ANG, Thow-Pang CHONG, Dan MANSUR, Ali BURNEY
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Patent number: 7434192Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.Type: GrantFiled: December 13, 2004Date of Patent: October 7, 2008Assignee: Altera CorporationInventors: Darren van Wageningen, Curt Wortman, Boon-Jin Ang, Thow-Pang Chong, Dan Mansur, Ali Burney
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Patent number: 7363526Abstract: A method for transferring data across different clock domains is provided. The method initiates with detecting a transition of a first clock cycle. The method includes propagating a value associated with the transition of the first clock cycle according to a second clock cycle. The propagation of the value causes a delay of a signal configured to trigger transfer of the data to a logic region operating at the second clock cycle. An interfacing circuit and a programmable logic device are also provided.Type: GrantFiled: September 7, 2004Date of Patent: April 22, 2008Assignee: Altera CorporationInventors: Thow Pang Chong, Boon Jin Ang
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Patent number: 7242218Abstract: Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.Type: GrantFiled: December 2, 2004Date of Patent: July 10, 2007Assignee: Altera CorporationInventors: Rafael Camarota, Irfan Rahim, Boon Jin Ang, Thow Pang Chong
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Patent number: 7233189Abstract: Signal transmission circuitry on an integrated circuit ameliorates the effects of possible inequality in rise and fall times of buffer circuits along the transmission circuitry by providing at least one of the buffer circuits as an inverting buffer circuit and at least one other of the buffer circuits as a non-inverting buffer circuit. The invention may be of particular interest for use in clock signal distribution networks on integrated circuits such as programmable logic devices.Type: GrantFiled: November 24, 2004Date of Patent: June 19, 2007Assignee: Altera CorporationInventors: Boon Jin Ang, Thow Pang Chong
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Publication number: 20060125517Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.Type: ApplicationFiled: December 13, 2004Publication date: June 15, 2006Applicant: Altera CorporationInventors: Darren van Wageningen, Curt Wortman, Boon-Jin Ang, Thow-Pang Chong, Dan Mansur, Ali Burney