Abstract: Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.

Abstract: A method and circuit for reducing a glitch in a memory read latch is disclosed. A read latch circuit includes a first logic gate having a first input coupled to a read bit line and a second input. The read latch circuit further includes a second logic gate coupled to receive as inputs a first enable signal and a delayed version of the first enable signal. The second logic gate is configured to provide a second enable signal to the second input of the first logic gate. The second logic gate is configured to provide a rising edge of the second enable signal after a predetermined delay without a corresponding delay of a falling edge of the second enable signal. The first logic gate provides an output corresponding to a data value received on the read bit line responsive to receiving the rising edge of the second enable signal.

Abstract: Systems, methods, and other embodiments associated with controlling when a sense amplifier is activated are described. In one embodiment, a device includes detection logic connected to a plurality of word lines in a memory and configured to generate a signal upon detecting one of the plurality of word lines being activated. The device includes a sense amplifier configured to read a value from a bit line associated with an activated word line of the plurality of word lines upon receiving the signal.