Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

Abstract: In one example, a system comprises an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns; and a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator comprising a voltage ladder to generate a plurality of voltages according to a logarithmic formula.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.

Abstract: In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

Abstract: A system and method for facilitating connecting a switch to a network to improve network performance. In an illustrative embodiment, the system includes a first module for determining when the switch is initially connected to a network and providing a signal in response thereto. A second module selectively forms adjacencies with peers of the switch in response to the signal and based on one or more predetermined parameters. In a more specific embodiment, the switch is a router or Layer-3 (L3) switch. The one or more predetermined parameters include a load factor, values pertaining to capabilities of a processor included in the router, bandwidth capabilities of the interface and/or the router, internal router queue counts, and so on. The router employs a routing protocol such as Enhanced Interior Gateway Routing Protocol (EIGRP). The second module throttles and adjacency-formation rate based on the predetermined parameters.

Abstract: A system and method for facilitating connecting a switch to a network to improve network performance. In an illustrative embodiment, the system includes a first module for determining when the switch is initially connected to a network and providing a signal in response thereto. A second module selectively forms adjacencies with peers of the switch in response to the signal and based on one or more predetermined parameters. In a more specific embodiment, the switch is a router or Layer-3 (L3) switch. The one or more predetermined parameters include a load factor, values pertaining to capabilities of a processor included in the router, bandwidth capabilities of the interface and/or the router, internal router queue counts, and so on. The router employs a routing protocol such as Enhanced Interior Gateway Routing Protocol (EIGRP). The second module throttles and adjacency-formation rate based on the predetermined parameters.

Abstract: Techniques are disclosed for synchronizing a database related to a first node in a network with multiple nodes. Each node includes a database different from a database on a different node. An inquiry control message is sent to each node in a candidate set of one or more nodes on the network, which are different from the first node. In response to the inquiry control message, the first node receives a first set of one or more messages from a particular node different from the first node. The first set indicates a portion from the database of the particular node. The portion is relevant for the first node. A particular portion of a first database for the first node is derived from the first set of messages. The particular portion is less than all of the first database. These techniques allow the first node to derive its full database from multiple adjacent nodes.

Abstract: A system and method for facilitating connecting a switch to a network to improve network performance. In an illustrative embodiment, the system includes a first module for determining when the switch is initially connected to a network and providing a signal in response thereto. A second module selectively forms adjacencies with peers of the switch in response to the signal and based on one or more predetermined parameters. In a more specific embodiment, the switch is a router or Layer-3 (L3) switch. The one or more predetermined parameters include a load factor, values pertaining to capabilities of a processor included in the router, bandwidth capabilities of the interface and/or the router, internal router queue counts, and so on. The router employs a routing protocol such as Enhanced Interior Gateway Routing Protocol (EIGRP). The second module throttles and adjacency-formation rate based on the predetermined parameters.

Abstract: A system for optimizing the performance of a network. In an illustrative embodiment, the system includes a memory containing one or more data structures data structures. A first module determines transit-only information. A second module selectively omits the transit-only information from the one or more data structures. In a more specific embodiment, the one or more data structures include one or more tables. The transit-only information includes interface Internet Protocol (IP) addresses associated with network interfaces that are transit-only interfaces. The route information may include network topology information. The one or more tables may include a network topology table. Plural routers positioned in the network incorporate one or more instances of the system. The routers may employ one or more routing protocols, such as include Enhanced Interior Gateway Routing Protocol (EIGRP) or Routing Information Protocol (RIP).

Abstract: A system and method for enhancing the behavior of a network. In an illustrative embodiment, the network includes a distribution router and plural additional routers connected to the distribution router. The system includes a first module that is adapted to characterize the additional routers as stub routers or non-stub routers and then to provide a signal in response thereto. A second module selectively queries non-stub routers for route information and does not query stub routers for the route information. In a more specific embodiment, the second module includes a unicast module for selectively unicasting queries to the non-stub routers. A multicast module selectively multicasts queries to the non-stub routers via a modified conditional-receive algorithm.