Patents by Inventor Thungoc M. Tran
Thungoc M. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9405865Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system.Type: GrantFiled: December 18, 2013Date of Patent: August 2, 2016Assignee: Altera CorporationInventors: Peng Li, Masashi Shimanouchi, Thungoc M. Tran, Sergey Shumarayev
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Patent number: 9383763Abstract: In one embodiment, an integrated circuit current mirror circuit is disclosed. The integrated circuit current mirror circuit includes a reference circuit, an output circuit and a mode selector circuit. The reference circuit includes an input terminal that receives a reference current. The output circuit generates an output current that is proportional to the reference current. The output circuit is coupled to a load circuit. The output current is provided to the load circuit. The mode selector circuit is coupled to the reference circuit and the output circuit. The mode selector circuit receives a plurality of mode control signals having different voltage levels. The mode selector circuit selects one of the mode control signals. The selected mode control signal is routed to the reference circuit and the output circuit to place the current mirror circuit in a desired mode.Type: GrantFiled: January 3, 2014Date of Patent: July 5, 2016Assignee: Altera CorporationInventors: Xiong Liu, Thungoc M. Tran, Tim Tri Hoang, Wilson Wong, Vishal Giridharan
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Patent number: 9094239Abstract: Among other things, the present invention addresses timing issues related to a polarity control scheme in DFE implementation. Multiplexing that may be necessary for implementing a polarity control scheme is incorporated into multiplexing that may be required to convert half rate data into full rate data in a delay element of a DFE. Clocking signals are provided to a multiplexer that are encoded with polarity information. The various clock signals are generated using a clock generation circuit that incorporates polarity control.Type: GrantFiled: October 1, 2012Date of Patent: July 28, 2015Assignee: Altera CorporationInventors: Mei Luo, Thungoc M. Tran
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Patent number: 9077330Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: September 10, 2013Date of Patent: July 7, 2015Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Patent number: 9030244Abstract: An integrated circuit includes a duty cycle detection circuit, a comparator circuit, and a tuning circuit. The duty cycle detection circuit receives a clock signal, such as a system clock signal, and detects the level of duty cycle distortion in the clock signal. The comparator circuit then generates an output based on the level of duty cycle distortion that is detected in the clock signal. The tuning circuit may accordingly adjust the clock signal based on the output generated by the comparator circuit to produce an adjusted clock output signal. As an example, the clock output signal produced by the tuning circuit after the adjustment may have a 50% (or significantly close to 50%) duty cycle.Type: GrantFiled: January 15, 2014Date of Patent: May 12, 2015Assignee: Altera CorporationInventors: Mei Luo, Allen K. Chan, Thungoc M. Tran
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Patent number: 8976804Abstract: In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.Type: GrantFiled: March 7, 2011Date of Patent: March 10, 2015Assignee: Altera CorporationInventors: Sergey Shumarayev, Wilson Wong, Thungoc M. Tran, Tim Tri Hoang
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Patent number: 8837571Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.Type: GrantFiled: August 2, 2013Date of Patent: September 16, 2014Assignee: Altera CorporationInventors: Yanjing Ke, Thungoc M Tran, Weiqi Ding, Jie Shen, Xiong Liu, Sangeeta Raman, Peng Li
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Patent number: 8705602Abstract: Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).Type: GrantFiled: October 16, 2009Date of Patent: April 22, 2014Assignee: Altera CorporationInventors: Weiqi Ding, Mengchi Liu, Mingde Pan, Thungoc M. Tran, Sergey Shumarayev
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Publication number: 20140107997Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: Altera CorporationInventors: Peng Li, Masashi Shimanouchi, Thungoc M. Tran, Sergey Shumarayev
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Publication number: 20140009188Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc M. Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong H. Lee
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Patent number: 8626474Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system.Type: GrantFiled: April 19, 2010Date of Patent: January 7, 2014Assignee: Altera CorporationInventors: Peng Li, Masashi Shimanouchi, Thungoc M. Tran, Sergey Shumarayev
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Patent number: 8619931Abstract: Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.Type: GrantFiled: November 19, 2009Date of Patent: December 31, 2013Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Tim Tri Hoang, Thungoc M. Tran, Vinh Van Ho, Leon Zheng
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Patent number: 8571059Abstract: Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.Type: GrantFiled: July 29, 2011Date of Patent: October 29, 2013Assignee: Altera CorporationInventors: Arch Zaliznyak, Ramanand Venkata, Surinder Singh, Henry Y. Lui, Tim Tri Hoang, Sergey Shumarayev, Thungoc M. Tran
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Patent number: 8464088Abstract: Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair.Type: GrantFiled: October 29, 2010Date of Patent: June 11, 2013Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Sergey Shumarayev, Tim Tri Hoang, Weiqi Ding, Thungoc M. Tran
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Patent number: 8417752Abstract: An equalizer circuitry that includes an equalizer stage having a programmable current source is described. In one implementation, the programmable current source cancels voltage offset. Also, in one implementation, the programmable current source is programmable in user mode. Furthermore, in one implementation, the equalizer circuitry includes a plurality of equalizer stages including the equalizer stage having a programmable current source, where the equalizer stage having a programmable current source is a second equalizer stage in the plurality of equalizer stages. Also, in one implementation, the programmable current source includes a plurality of current sources coupled in parallel and a plurality of sets of control switches for controlling the plurality of current sources.Type: GrantFiled: May 21, 2009Date of Patent: April 9, 2013Assignee: Altera CorporationInventors: Doris Po Ching Chan, Simardeep Maangat, Thungoc M. Tran, Sergey Shumarayev
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Patent number: 8416898Abstract: A circuit includes a receiver circuit, a decision feedback equalizer circuit, and a control loop circuit. The receiver circuit receives a data signal and generates an input signal in response to the data signal. The decision feedback equalizer circuit includes a tap driver and a first current source coupled to the tap driver. The tap driver drives the input signal based on a tap weight. The control loop circuit varies a current through the first current source based on variations in the input signal to reduce changes in the tap weight that are caused by the variations in the input signal.Type: GrantFiled: June 11, 2009Date of Patent: April 9, 2013Assignee: Altera CorporationInventors: Mei Luo, Thungoc M. Tran, Tim Tri Hoang, Tin H. Lai
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Patent number: 8406258Abstract: One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer.Type: GrantFiled: April 1, 2010Date of Patent: March 26, 2013Assignee: Altera CorporationInventors: Wilson Wong, Tim Tri Hoang, Thungoc M. Tran, Sergey Shumarayev, Allen Chan
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Patent number: 8391350Abstract: Decision feedback equalizer (“DFE”) circuitry bases determination of the coefficients that are used in its various taps on the algebraic sign of the current value of an error signal and prior serial data signal values output by the DFE circuitry. Use of such algebraic sign information (rather than full error signal values) greatly simplifies the circuitry needed to determine the tap coefficients. The DFE circuitry can be adaptive, i.e., such that it automatically adjusts the tap coefficients for changing serial data signal transmission conditions.Type: GrantFiled: September 3, 2010Date of Patent: March 5, 2013Assignee: Altera CorporationInventors: Doris Po Ching Chan, Thungoc M. Tran
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Patent number: 8290750Abstract: Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.Type: GrantFiled: February 28, 2011Date of Patent: October 16, 2012Assignee: Altera CorporationInventors: Wilson Wong, Allen Chan, Sergey Shumarayev, Thungoc M. Tran, Tim Tri Hoang, Weiqi Ding
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Patent number: 8228102Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.Type: GrantFiled: March 3, 2010Date of Patent: July 24, 2012Assignee: Altera CorporationInventors: Tien Duc Pham, Sergey Shumarayev, Richard G. Cliff, Tim Tri Hoang, Weiqi Ding, Sriram Narayan, Thungoc M. Tran, Kumara Tharmalingam