Patents by Inventor Thuong Truong
Thuong Truong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7725618Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.Type: GrantFiled: July 29, 2004Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, Peichun Peter Liu, Thuong Truong, Takeshi Yamazaki
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Patent number: 7613841Abstract: Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.Type: GrantFiled: June 7, 2006Date of Patent: November 3, 2009Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Shigehiro Asano, Thuong Truong
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Patent number: 7596665Abstract: The present invention provides a mechanism for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.Type: GrantFiled: October 18, 2007Date of Patent: September 29, 2009Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Johns, Thuong Truong
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Patent number: 7590802Abstract: The present invention provides a mechanism of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.Type: GrantFiled: October 19, 2007Date of Patent: September 15, 2009Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Johns, Thuong Truong
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Publication number: 20080040548Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.Type: ApplicationFiled: October 18, 2007Publication date: February 14, 2008Inventors: Michael Day, Charles Johns, Thuong Truong
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Publication number: 20080040549Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.Type: ApplicationFiled: October 19, 2007Publication date: February 14, 2008Inventors: Michael Day, Charles Johns, Thuong Truong
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Publication number: 20070288672Abstract: Systems and methods for enforcing in-order execution of commands sent from a master device to a slave device, where it is not necessary to provide a data buffer to store data associated with commands that are delayed to enforce in-order execution. In one embodiment, when a slave receives an execution synchronization command from a master, it determines whether its command queue contains unissued commands associated with master. If the command queue contains unissued commands, the slave issues a retry responsive to the execution synchronization command. If the command queue does not contain unissued commands, the slave issues an acknowledgment responsive to the execution synchronization command. The master will retry the execution synchronization command until the previous commands have been completed. Because the slave does not queue up any commands that would be delayed by the execution synchronization command, it does not have to provide space to store any associated data.Type: ApplicationFiled: June 7, 2006Publication date: December 13, 2007Inventors: Shigehiro Asano, Thuong Truong
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Patent number: 7290106Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.Type: GrantFiled: October 28, 2004Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Johns, Thuong Truong
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Patent number: 7290107Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.Type: GrantFiled: October 28, 2004Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Johns, Thuong Truong
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Publication number: 20070174556Abstract: In a first aspect, a first method of reducing reissue latency of a command received in a command processing pipeline from one of a plurality of units coupled to a bus is provided. The first method includes the steps of (1) from a first unit coupled to the bus, receiving a first command on the bus requiring access to a cacheline; (2) determining a state of the cacheline required by the first command by accessing cacheline state information stored in each of the plurality of units; (3) determining whether a second command received on the bus requires access to the cacheline before the state of the cacheline is returned to the first unit; and (4) if so, storing the second command in a buffer. Numerous other aspects are provided.Type: ApplicationFiled: January 26, 2006Publication date: July 26, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Brown, Michael Carnevale, Charles Johns, David Krolak, Thuong Truong
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Publication number: 20070174509Abstract: The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.Type: ApplicationFiled: April 2, 2007Publication date: July 26, 2007Inventors: Michael Day, Harm Hofstee, Charles Johns, Peichum Liu, Thuong Truong, Takeshi Yamazaki
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Patent number: 7243200Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.Type: GrantFiled: July 15, 2004Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Michael Norman Day, Charles Ray Johns, Peichun Peter Liu, Thuong Truong, Takeshi Yamazaki
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Publication number: 20070118837Abstract: A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.Type: ApplicationFiled: November 21, 2005Publication date: May 24, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard Doing, John Patty, Steven Testa, Thuong Truong
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Publication number: 20070079018Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: ApplicationFiled: August 19, 2005Publication date: April 5, 2007Inventors: Michael Day, Charles Johns, Peichun Liu, Todd Swanson, Thuong Truong
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Publication number: 20070041403Abstract: A system and method for communicating instructions and data between a processor and external devices are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.Type: ApplicationFiled: August 19, 2005Publication date: February 22, 2007Inventors: Michael Day, Charles Johns, John Liberty, Todd Swanson, Thuong Truong
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Method to Provide Atomic Update Primitives in an Asymmetric Heterogeneous Multiprocessor Environment
Publication number: 20070016733Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.Type: ApplicationFiled: August 30, 2006Publication date: January 18, 2007Inventors: Michael Day, Charles Johns, James Kahle, Peichum Liu, Thuong Truong -
Publication number: 20060253661Abstract: The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.Type: ApplicationFiled: May 3, 2005Publication date: November 9, 2006Applicant: International Business Machines CorporationInventors: Brian Bass, Thomas Jeremiah, Charles Johns, David Shippy, Thuong Truong
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Publication number: 20060253662Abstract: A method, an apparatus, and a computer program are provided for a retry cancellation mechanism to enhance system performance when a cache is missed or during direct memory access in a multi-processor system. In a multi-processor system with a number of independent nodes, the nodes must be able to request data that resides in memory locations on other nodes. The nodes search their memory caches for the requested data and provide a reply. The dedicated node arbitrates these replies and informs the nodes how to proceed. This invention enhances system performance by enabling the transfer of the requested data if an intervention reply is received by the dedicated node, while ignoring any retry replies. An intervention reply signifies that the modified data is within the node's memory cache and therefore, any retries by other nodes can be ignored.Type: ApplicationFiled: May 3, 2005Publication date: November 9, 2006Inventors: Brian Bass, James Dieffenderfer, Thuong Truong
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Publication number: 20060095668Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.Type: ApplicationFiled: October 28, 2004Publication date: May 4, 2006Applicant: International Business Machines CorporationInventors: Michael Day, Charles Johns, Thuong Truong
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Publication number: 20060095669Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.Type: ApplicationFiled: October 28, 2004Publication date: May 4, 2006Applicant: International Business Machines CorporationInventors: Michael Day, Charles Johns, Thuong Truong