Abstract: A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

Abstract: A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

Abstract: A wine-making pressing and fermenting apparatus that contains a compression-fermentation tank and a press plate moveable relative to the bottom of the tank due to engagement of a lead screw with a nut. According to one embodiment, the nut is fixed to the press tube that extends downward from the tank cover and engages the lead screw threaded into the nut from below and driven into rotation by the motor located under the tank in the tank supporting structure. According to another embodiment, the nut is fixed to the tank tube that extends upward from the tank bottom and engages the lead screw threaded into the nut from above and driven into rotation by the motor located over the tank and supported by the tank cover. The press plate has a plurality of through openings for squeezing out the grape juice.

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current ISTBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.

Abstract: A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention processes a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Abstract: In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Abstract: In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: A method of performing back-end manufacturing of an integrated circuit (IC) device is disclosed. In one method embodiment, the present invention process a die-strip through a front-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The die-strip is then automatically provided to an end-of-line assembly portion. The die-strip is then processed through an end-of-line assembly portion which comprises a plurality of sub-stations operating on an in-line basis. The present embodiment then automatically provides the die-strip to a test assembly portion. The die-strip is then tested by the test portion and then automatically provided to a finish assembly portion. The present embodiment then processes the die-strip through a finish portion which comprises a plurality of sub-stations operating on an in-line basis. Camera systems perform automated visual inspection of dies on the die-strip and maintain a database that can be used for automated reject management.

Abstract: A novel wine making apparatus includes an engaging mechanism for engaging a fermentation tank, and a press mechanism for pressing the wine making ingredients in the tank against an inner surface of the tank. In a particular embodiment, the engaging mechanism includes a tray for receiving the tank, and the press mechanism includes a press plate for pressing the contents of the tank against an inner surface of the tank. The engaging mechanism is moveably coupled to the press plate, and the wine making apparatus includes at least one drive mechanism to move the tank with respect to the press plate, in order to press the ingredients within the tank. A novel method of making wine is also disclosed, and includes loading a tank with ingredients, fermenting the ingredients in the tank to produce wine, and at least partially pressing the wine in the fermentation tank to separate the wine from solids.

Abstract: An integrated circuit and computer system. According to one embodiment of the present invention an integrated circuit on a single substrate for use with a microprocessor which is coupled to a processor bus is provided, and the integrated circuit includes a cache random access memory array and a data path logic control unit, such as multiplexer which is coupled to the cache random access memory array and has an output for coupling to the processor bus. In one embodiment, a further multiplexer having an output for coupling to a first portion of a memory is provided, and this multiplexer further has input for coupling to a second portion of the memory bus. The IC according the present invention is also for use with a second IC which includes control logic for controlling system memory and for controlling the processor bus and memory bus as well as interfacing to other buses such as peripheral bus.

Abstract: A process for minimizing bird's beak in local oxidation of silicon which is compatible with high density (VLSI) semiconductor devices is disclosed. A pad oxide is nitridized using rapid thermal nitridization, which works quickly with minimal thermal cycling of the wafer. A silicon nitride film is then deposited over the nitridized oxide. Both films are exposed to dry plasma etching which gives more consistent results than wet methods. The field oxide is then grown and finally the masking films of the nitridized oxide and silicon nitride are removed, whereby field oxides are grown with minimal bird's beak, and minimal damage to the wafer with a small number of steps. The pad oxide may be grown in the same rapid thermal annealer used for the rapid thermal nitridization. Both cycles (pad oxide growth and nitridization of the pad oxide) can be integrated to "one" cycle and performed sequentially in the same rapid thermal annealer to increase throughput and improve device quality.

Abstract: A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

Abstract: A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device).

Abstract: An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.