Patents by Inventor Ti Ching Shian

Ti Ching Shian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip chip MLP with conductive ink
    Patent number: 9147627
    Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: September 29, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
  • Semiconductor die package using leadframe and clip and method of manufacturing
    Patent number: 8058107
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: November 15, 2011
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • FLIP CHIP MLP WITH CONDUCTIVE INK
    Publication number: 20100052127
    Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.
    Type: Application
    Filed: November 12, 2009
    Publication date: March 4, 2010
    Inventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
  • Flip chip MLP with conductive ink
    Patent number: 7638861
    Abstract: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: December 29, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
  • SEMICONDUCTOR DIE PACKAGE USING LEADFRAME AND CLIP AND METHOD OF MANUFACTURING
    Publication number: 20080044946
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Application
    Filed: September 17, 2007
    Publication date: February 21, 2008
    Inventors: Erwin Victor Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Semiconductor die package using leadframe and clip and method of manufacturing
    Patent number: 7285849
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 23, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Semiconductor die package using leadframe and clip and method of manufacturing
    Publication number: 20070114352
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Application
    Filed: November 18, 2005
    Publication date: May 24, 2007
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer