Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

Abstract: A head-up display (HUD) device includes a display element, a first reflective element, and a second reflective element. The display element provides an image light beam that includes a first light beam and a second light beam, where the first light beam and the second light beam exit from different positions of the display element. The first reflective element is disposed on a transmission path of the image light beam coming from the display element to reflect the image light beam. The second reflective element is disposed on a transmission path of the image light beam coming from the first reflective element to reflect the image light beam. A primary ray of the first light beam and a primary ray of the second light beam exiting from the display element form an intersection point on the first reflective element or between the display element and the first reflective element.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first hardmask layer over a substrate, forming a second hardmask layer over the first hardmask layer, etching the second hardmask layer to form a pattern in the second hardmask layer, transferring the pattern to the first hardmask layer, removing the second hardmask layer and trimming an upper portion of the pattern in the first hardmask layer, forming a silicon-containing layer on a top surface of the pattern in the first hardmask layer, and etching the substrate with the pattern in the first hardmask layer and the silicon-containing layer both serving as a mask.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.

Abstract: A method for processing a substrate that includes: patterning a carbon-based hardmask layer over a dielectric layer to form a first recess in the carbon-based hardmask layer, the first recess having a tapered profile such that a width of the first recess at a first height is greater than a width of the first recess at a second height that is lower than the first height; depositing a metal-containing layer over the patterned carbon-based hardmask layer, the metal-containing layer being physically in contact with sidewalls of the patterned carbon-based hardmask layer in the first recess, the metal-containing layer being thicker at the first height than at the second height; and etching the dielectric layer using the patterned carbon-based hardmask layer as an etch mask by an anisotropic plasma etch process to form a second recess in the dielectric layer.

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor on a substrate, a contact electrically connected to a source/drain feature of the transistor, a first dielectric layer on a gate stack of the transistor, a second dielectric layer on the contact, a gate spacer layer between the gate stack of the transistor and the contact, and a contact liner between the gate spacer layer and the contact. A top of the contact liner is located higher than a bottom surface of the second dielectric layer and lower than a top surface of the second dielectric layer.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A grinding apparatus and a crystal orientation adjustment fixture thereof are provided. The crystal orientation adjustment fixture includes a fixing seat, an adjustment body, a first adjustment component, and a universal mandrel module. The adjustment body is assembled to the fixing seat through a rear end surface thereof. The adjustment body has a universal slot recessed in a front end surface thereof and a first adjustment slot formed along an adjustment direction, and a bottom of the first adjustment slot corresponds in position to the fixing seat. The first adjustment component is movably assembled in the first adjustment slot along the adjustment direction and abuts against the fixing seat. The universal mandrel module is rotatably assembled in the universal slot. The first adjustment component is adjustable along the adjustment direction to move the adjustment body relative to the fixing seat along the adjustment direction.

Abstract: A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Abstract: A semiconductor structure includes a metal gate structure, a first gate spacer disposed on a first side of the metal gate structure, a source/drain feature disposed adjacent to the first gate spacer, a dielectric structure disposed over the source/drain feature, the first gate spacer, and the metal gate structure, and a contact feature disposed in the dielectric structure and electrically connected to the metal gate structure and the source/drain feature. The first gate spacer is between the source/drain feature and the metal gate structure. The contact feature straddles over the first gate spacer and has a tilted sidewall intersecting with the metal gate structure.

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

Abstract: A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.