Abstract: A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first control signal and thus controls a voltage level of a third control signal. The switch device receives the second and third control signals and respectively couples an output terminal to a first external voltage source and a second external voltage source when the second and third control signals are enabled. When the enable signal is disabled, the second and third control signals are simultaneously disabled so that the output terminal is floating with respect to the first and second external voltage sources and the output terminal is held in a high impedance state.

Abstract: A method of manufacturing, programming and reading a non-volatile memory is provided. First, a to-be-coded memory having a plurality of to-be-coded cells arranged in a array is provided. Next, an implanting resist layer is formed on the to-be-coded memory. Then, a mask is disposed on the to-be-coded memory, wherein the number of the partial to-be-coded cells under the openings of the mask is less than the number of remaining to-be-coded cells. Afterwards, a patterned implanting resist layer is formed according to the mask. Next, the exposed to-be-coded cells are ion-implanted to define a plurality of first cells and second cells, wherein each first cell and each second cell record a second bit state and a first bit state respectively. Then, the to-be-coded memory is inversely defined, such that the first cells and the second cells record the first bit state and the second bit state respectively.

Abstract: A rapid equalizing ground line and sense circuit. The ground line Circuit includes a reference transistor and a plurality of switching circuits. When the ground line signal is disabled, corresponding ground line of the switching circuit couples with the pre-charging bus to initiate a pre-charging operation. If the selected ground line signal is enabled, the selected switching circuit initiates a data sensing operation. If the selected ground line signal is disabled, the corresponding ground line of non-selected switching circuits continues to pre-charge. When the selected ground line signal changes from an enable state to a disable state, the corresponding ground line of the selected switching circuit and corresponding ground line of the non-selected switching circuit are coupled to a voltage source.

Abstract: A current mirror sense amplifier, with a two-stage current mirror, a first transistor, and a second transistor. The first transistor and the second transistor each have first and second connection terminals. The current mirror has a current input terminal and a current output terminal. The first transistor has a gate electrically connected to a pre-charge voltage. The first connection terminal of the first transistor is electrically connected to a reference voltage. The second transistor has a gate electrically connected to a reference signal. The first connection terminal of the second transistor is electrically connected to the reference voltage. The second connection terminals are connected to the current output terminal in parallel.