Patents by Inventor Tiago Diadami Perez

Tiago Diadami Perez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Optimized CORDIC for APSK applications
    Patent number: 10320595
    Abstract: A reduced COordinate Rotation DIgital Computer (CORDIC) cell in a parallel CORDIC has an xy-path from x and y inputs to x and y outputs, and a z-path from a z-input to a z-output. Bit-shifts in the xy-path are hardwired. The z-path has a shortened adder/subtractor with a built-in or hardwired fixed parameter. Input bits from the z-input are split into most significant and least significant bits. The number of most significant bits equals the shortened adder/subtractor width. The most significant bits are input to the non-inverting inputs of the adder/subtractor for calculating the most significant z-output bits. The least significant bits are connected directly (or via buffers) from the z-input to the z-output.
    Type: Grant
    Filed: June 17, 2018
    Date of Patent: June 11, 2019
    Assignee: Instituto de Pesquisas Eldorado
    Inventors: Eduardo Rodrigues de Lima, Tiago Diadami Perez
  • Optimized CORDIC for APSK Applications
    Publication number: 20180375699
    Abstract: A reduced COordinate Rotation DIgital Computer (CORDIC) cell in a parallel CORDIC has an xy-path from x and y inputs to x and y outputs, and a z-path from a z-input to a z-output. Bit-shifts in the xy-path are hardwired. The z-path has a shortened adder/subtractor with a built-in or hardwired fixed parameter. Input bits from the z-input are split into most significant and least significant bits. The number of most significant bits equals the shortened adder/subtractor width. The most significant bits are input to the non-inverting inputs of the adder/subtractor for calculating the most significant z-output bits. The least significant bits are connected directly (or via buffers) from the z-input to the z-output.
    Type: Application
    Filed: June 17, 2018
    Publication date: December 27, 2018
    Applicant: Instituto de Pesquisas Eldorado
    Inventors: Eduardo Rodrigues de Lima, Tiago Diadami Perez