Patents by Inventor Tiam Hock Tan

Tiam Hock Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7324982
    Abstract: A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge framework and automates the formulation of a valid stable, and preferably optimized, test for execution on an integrated circuit tester.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: January 29, 2008
    Assignee: Agilent Technologies, Inc.
    Inventors: Aik Koon Loh, Keen Fung Wai, Tiam Hock Tan, Roy H. Williams
  • Publication number: 20070013362
    Abstract: A method and apparatus for maximizing the usage of a testhead of an in-circuit tester is presented. A testhead execution supervisor interfaces between a testhead controller and a graphical user interface used to enter manual tests. The testhead execution supervisor adds tests to be submitted to the testhead to one or more queues according to a priority scheme. Tests may be submitted to the testhead execution supervisor both as manual tests entered via the graphical user interface and as automatically generated tests generated by an automatic debug module. The automatic debug module may automatically generate tests for execution by the testhead that are executed when the testhead is idle, for example when no higher priority manual tests are scheduled.
    Type: Application
    Filed: July 18, 2005
    Publication date: January 18, 2007
    Inventors: Aik Loh, Roy Williams, Keen Fung Wai, Chen Low, Yi Jin, Rex Shang, Tiam Hock Tan, Daniel Whang
  • Patent number: 7089139
    Abstract: A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an integrated circuit tester. In a system that includes a rule-based controller for controlling interaction between the test-head controller of an integrated circuit tester and an automated debug system, the invention includes a knowledge framework and a rule-based editor. The knowledge framework stores test knowledge in the representation of rules that represent a debugging strategy. The rule-based editor facilitates the use of rules as knowledge to debug or optimize an in-circuit test that is to be executed on the integrated circuit tester.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: August 8, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Aik Koon Loh, Keen Fung Wai, Tiam Hock Tan, Roy H. Williams, Daniel Z. Whang, Chen Ni Low, Ellis Yuan