Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.

Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.

Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.

Abstract: A method of determining the deposition temperature, especially inside the reaction chamber of a chemical vapor deposition station. The method includes placing a deposition substrate inside the reaction chamber, forming a layer of metal silicide over the deposition substrate, measuring the silicon/metal atomic ratio and finding the deposition temperature according to a pre-determined temperature versus silicon/metal atomic ratio relationship. The method permits immediate determination as well as real-time monitoring of deposition temperature inside the station.

Abstract: An etching method with less waste gases. Firstly, provide a substrate covered by a dielectric layer, and put both the substrate and the dielectric layer into a chamber that is coupled with a power source and a C3F8 reactive gases source. Next, provide a plasma inside the chamber under an environment with a low RF power, and a low pressure. Finally, terminate the existence of the plasma and move both the substrate and the etched dielectric later out the chamber.