Patents by Inventor Tian Lu
Tian Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260012161Abstract: A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value “1” or “0” a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.Type: ApplicationFiled: June 21, 2023Publication date: January 8, 2026Inventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick
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Publication number: 20240265996Abstract: The present invention generally relates to systems and methods for imaging or determining nucleic acids or other desired targets, for instance, within cells or tissues. In one aspect, a sample is exposed to a plurality of nucleic acid probes that are determined within the sample. In some cases, however, background fluorescence or off-target binding may make it more difficult to determine properly bound nucleic acid probes. Accordingly, other components of the samples that may be contributing to the background, such as proteins, lipids, and/or other non-targets, may be “cleared” from the sample to improve determination. However, in certain embodiments, nucleic acids or other desired targets may be prevented from also being cleared, e.g., using polymers or gels within the sample. Other aspects are generally directed to compositions or kits involving such systems, methods of using such systems, or the like.Type: ApplicationFiled: December 21, 2023Publication date: August 8, 2024Applicant: President and Fellows of Harvard CollegeInventors: Xiaowei Zhuang, Jeffrey R. Moffitt, Junjie George Hao, Tian Lu
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Publication number: 20240112755Abstract: The present invention generally relates to systems and methods for imaging or determining nucleic acids or other desired targets, for instance, within cells or tissues. In one aspect, a sample is exposed to a plurality of nucleic acid probes that are determined within the sample. In some cases, however, background fluorescence or off-target binding may make it more difficult to determine properly bound nucleic acid probes. Accordingly, other components of the samples that may be contributing to the background, such as proteins, lipids, and/or other non-targets, may be “cleared” from the sample to improve determination. However, in certain embodiments, nucleic acids or other desired targets may be prevented from also being cleared, e.g., using polymers or gels within the sample. Other aspects are generally directed to compositions or kits involving such systems, methods of using such systems, or the like.Type: ApplicationFiled: May 1, 2023Publication date: April 4, 2024Applicant: President and Fellows of Harvard CollegeInventors: Xiaowei Zhuang, Jeffrey R. Moffitt, Junjie George Hao, Tian Lu
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Patent number: 11523511Abstract: A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.Type: GrantFiled: February 3, 2021Date of Patent: December 6, 2022Assignee: Indiana Integrated Circuits, LLCInventors: Jason M. Kulick, Tian Lu
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Patent number: 11488660Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.Type: GrantFiled: February 19, 2021Date of Patent: November 1, 2022Assignees: INDIANA INTEGRATED CIRCUITS, LLC, UNIVERSITY OF NOTRE DAME DU LACInventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick
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Patent number: 11398463Abstract: A method of forming a quilt package nodule includes forming a trench in a microchip substrate, forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides. forming a mask layer on the metal layer, removing portions of the mask and metal layers on the bottom of the trench, etching the bottom of the trench to increase the depth of the bottom of the trench, removing remaining portions of the mask layer from the metal layer to define the quilt package nodules that protrude beyond edges of the first and second sides, and removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule protruding from the side.Type: GrantFiled: November 4, 2020Date of Patent: July 26, 2022Assignee: Indiana Integrated Circuits, LLCInventors: Jason M. Kulick, Tian Lu
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Publication number: 20220205983Abstract: The present invention generally relates to imaging cells, for example, to determine phenotypes and/or genotypes in populations of cells, e.g., to build genotype-phenotype corresponse for high-throughput screening. In some cases, the cells may be manipulated, e.g., using CRISPR or other techniques. In certain embodiments, nucleic acids may be introduced to the cell, e.g., using a lentivirus. The nucleic acids may contain a guide portion comprising a DNA or RNA recognition sequence, a reporter portion, and an identification portion comprising one or more read sequences. The guide portion may be used to alter the phenotype of the cells, e.g., using a sequence, e.g., an sgRNA sequence, that can be targeted using CRISPR or other techniques, and in some cases, the phenotype of the cells may be determined using various imaging approaches. The identification portion may be determined using MERFISH or other suitable techniques.Type: ApplicationFiled: April 17, 2020Publication date: June 30, 2022Applicant: President and Fellows of Harvard CollegeInventors: Xiaowei Zhuang, Chong Wang, Tian Lu
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Patent number: 11224126Abstract: A substrate assembly includes at least one printed circuit (PC) substrate. Each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface. The edge includes or defines on a facet or edge surface of the edge at least one projection that extends transverse or normal to the facet or edge surface. The projection includes a projection top surface and a projection bottom surface spaced from each other and the projection can include or be made of conductive material.Type: GrantFiled: January 9, 2020Date of Patent: January 11, 2022Assignees: Indiana Integrated Circuits, LLC, Science Applications International CorporationInventors: Jason M. Kulick, Tian Lu, Carlos J. Ortega, Robert Joseph Engelhardt, Jr., John Philip Timler
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Publication number: 20210383218Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining a control policy for an agent interacting with an environment. One of the methods includes updating the control policy using policy-consistent backups using Q learning. To determine a policy-consistent backup, the system determining a policy-consistent backup for the control policy at the current observation—current action pair, comprising: for each of a plurality of actions in a set of possible actions that can be performed by the agent, identifying Q values assigned by the control policy to next observation—action pairs by the control policy and justified by at least one of the information sets; pruning, from the identified Q values, any Q values that are justified only by information sets that are not policy-class consistent; and determining, from the reward and only the identified Q values that were not pruned, the policy-consistent backup.Type: ApplicationFiled: October 29, 2019Publication date: December 9, 2021Inventors: Tian Lu, Dale Eric Schuurmans, Craig Edgar Boutilier
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Publication number: 20210327496Abstract: In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time T1 whereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T2, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time T1 and/or time T2 is/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.Type: ApplicationFiled: February 19, 2021Publication date: October 21, 2021Inventors: Gregory Snider, Rene Celis-Cordova, Alexei Orlov, Tian Lu, Jason M. Kulick
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Publication number: 20210168938Abstract: A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.Type: ApplicationFiled: February 3, 2021Publication date: June 3, 2021Inventors: Jason M. Kulick, Tian Lu
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Patent number: 10945335Abstract: Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.Type: GrantFiled: November 20, 2017Date of Patent: March 9, 2021Assignee: Indiana Integrated Circuits, LLCInventors: Jason M. Kulick, Tian Lu
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Publication number: 20210050335Abstract: A method of forming a quilt package nodule includes forming a trench in a microchip substrate, forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides. forming a mask layer on the metal layer, removing portions of the mask and metal layers on the bottom of the trench, etching the bottom of the trench to increase the depth of the bottom of the trench, removing remaining portions of the mask layer from the metal layer to define the quilt package nodules that protrude beyond edges of the first and second sides, and removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule protruding from the side.Type: ApplicationFiled: November 4, 2020Publication date: February 18, 2021Inventors: Jason M. Kulick, Tian Lu
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Publication number: 20210051799Abstract: A substrate assembly includes at least one printed circuit (PC) substrate. Each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface. The edge includes or defines on a facet or edge surface of the edge at least one projection that extends transverse or normal to the facet or edge surface. The projection includes a projection top surface and a projection bottom surface spaced from each other and the projection can include or be made of conductive material.Type: ApplicationFiled: January 9, 2020Publication date: February 18, 2021Inventors: Jason M. Kulick, Tian Lu, Carlos J. Ortega, Robert Joseph Engelhardt, Jr., John Philip Timler
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Patent number: 10896898Abstract: A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.Type: GrantFiled: October 25, 2016Date of Patent: January 19, 2021Assignee: Indiana Integrated Circuits, LLCInventors: Jason M. Kulick, Tian Lu
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Patent number: 10598861Abstract: Disclosed is a method and system for passively aligning optical fibers (4), a first waveguide array (62), and a second waveguide array (42) using chip-to-chip vertical evanescent optical waveguides (44) and (64), that can be used with fully automated die bonding equipment. The assembled system (2, 30, 60) can achieve high optical coupling and high process throughput for needs of high volume manufacturing of photonics, silicon photonics, and other applications that would benefit from aligning optical fibers to lasers efficiently.Type: GrantFiled: September 10, 2019Date of Patent: March 24, 2020Assignees: Indiana Integrated Circuits, LLC, MRSI Systems, LLC, Rochester Institute of TechnologyInventors: Jason M. Kulick, Yi Qian, Stefan Preble, Jeffrey Steidle, Michael Fanto, Tian Lu
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Publication number: 20200003955Abstract: Disclosed is a method and system for passively aligning optical fibers (4), a first waveguide array (62), and a second waveguide array (42) using chip-to-chip vertical evanescent optical waveguides (44) and (64), that can be used with fully automated die bonding equipment. The assembled system (2, 30, 60) can achieve high optical coupling and high process throughput for needs of high volume manufacturing of photonics, silicon photonics, and other applications that would benefit from aligning optical fibers to lasers efficiently.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Jason M. Kulick, Yi Qian, Stefan Preble, Jeffrey Steidle, Michael Fanto, Tian Lu
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Patent number: 10409004Abstract: Disclosed is a method and system for passively aligning optical fibers (4), a first waveguide array (62), and a second waveguide array (42) using chip-to-chip vertical evanescent optical waveguides (44) and (64), that can be used with fully automated die bonding equipment. The assembled system (2, 30, 60) can achieve high optical coupling and high process throughput for needs of high volume manufacturing of photonics, silicon photonics, and other applications that would benefit from aligning optical fibers to lasers efficiently.Type: GrantFiled: July 19, 2017Date of Patent: September 10, 2019Assignees: Indiana Integrated Circuits, LLC, MRSI Systems, LLC, Rochester Institute of TechnologyInventors: Jason M. Kulick, Yi Qian, Stefan Preble, Jeffrey Steidle, Michael Fanto, Tian Lu
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Publication number: 20190264270Abstract: The present invention generally relates to systems and methods for imaging or determining nucleic acids or other desired targets, for instance, within cells or tissues. In one aspect, a sample is exposed to a plurality of nucleic acid probes that are determined within the sample. In some cases, however, background fluorescence or off-target binding may make it more difficult to determine properly bound nucleic acid probes. Accordingly, other components of the samples that may be contributing to the background, such as proteins, lipids, and/or other non-targets, may be “cleared” from the sample to improve determination. However, in certain embodiments, nucleic acids or other desired targets may be prevented from also being cleared, e.g., using polymers or gels within the sample. Other aspects are generally directed to compositions or kits involving such systems, methods of using such systems, or the like.Type: ApplicationFiled: November 8, 2017Publication date: August 29, 2019Applicant: President and Fellows of Harvard CollegeInventors: Xiaowei Zhuang, Jeffrey R. Moffitt, Junjie George Hao, Tian Lu
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Publication number: 20190250335Abstract: Disclosed is a method and system for passively aligning optical fibers (4), a first waveguide array (62), and a second waveguide array (42) using chip-to-chip vertical evanescent optical waveguides (44) and (64), that can be used with fully automated die bonding equipment. The assembled system (2, 30, 60) can achieve high optical coupling and high process throughput for needs of high volume manufacturing of photonics, silicon photonics, and other applications that would benefit from aligning optical fibers to lasers efficiently.Type: ApplicationFiled: July 19, 2017Publication date: August 15, 2019Applicants: Indiana Integrated Circuits, LLC, Rochester Institute of Technology, MRSI Systems, LLCInventors: Jason M. KULICK, Yi QIAN, Stefan PREBLE, Jeffrey STEIDLE, Michael FANTO, Tian LU