Patents by Inventor Tian Shen TANG

Tian Shen TANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10204688
    Abstract: Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: February 12, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Jia Xu Peng, Hao Ni, Tian Shen Tang, Yao Zhou
  • Patent number: 10014768
    Abstract: A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 3, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yao Zhou, Hao Ni, Tian Shen Tang
  • Patent number: 10008246
    Abstract: A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 26, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Yao Zhou, Hao Ni, Tian Shen Tang, Tao Wang
  • Publication number: 20180061502
    Abstract: Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.
    Type: Application
    Filed: August 17, 2017
    Publication date: March 1, 2018
    Inventors: Jia Xu PENG, Hao NI, Tian Shen TANG, Yao ZHOU
  • Publication number: 20170330602
    Abstract: A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.
    Type: Application
    Filed: April 3, 2017
    Publication date: November 16, 2017
    Inventors: Yao ZHOU, Hao NI, Tian Shen TANG, Tao WANG
  • Publication number: 20170288532
    Abstract: A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.
    Type: Application
    Filed: February 17, 2017
    Publication date: October 5, 2017
    Inventors: Yao ZHOU, Hao NI, Tian Shen TANG