Abstract: Personal care formulation is provided having multistage polymer, comprising: acrylate rich stage comprising: (a) structural units of monomer selected from C1-22 alkyl (meth)acrylates and structural units of first carbosiloxane monomer of formula (I); and (b) carbosiloxane rich stage, comprising: structural units of second carbosiloxane monomer of formula (I); wherein a is 0 to 3; wherein d is 0 or 1; wherein R1 is selected from hydrogen, C1-10 alkyl group and aryl group; wherein R2 is selected from hydrogen and C1-10 alkyl group; wherein R8 is —O—Si(CH3)3 group; wherein Y is selected from formula (II), (III) and (IV); wherein R4 and R6 are selected from hydrogen and methyl group; wherein R3 and R5 are C1-10 alkylene group; wherein R7 is C1-10 alkyl group; wherein b is 0 to 4 and wherein c is 0 or 1; and wherein the first and second carbosiloxane monomer of formula (I) are same or different.

Abstract: A multistage polymer is provided, having: acrylate rich stage comprising: (a) structural units of monomer selected from C1-22 alkyl (meth)acrylates and structural units of first carbosiloxane monomer of formula (I); and (b) carbosiloxane rich stage, comprising: structural units of second carbosiloxane monomer of formula (I); wherein a is 0 to 3; wherein d is 0 or 1; wherein R1 is selected from hydrogen, C1-10 alkyl group and aryl group; wherein R2 is selected from hydrogen and C1-10 alkyl group; wherein R8 is —O—Si(CH3)3 group; wherein Y is selected from formula (II), (III) and (IV); wherein R4 and R6 are selected from hydrogen and methyl group; wherein R3 and R5 are a C1-10 alkylene group; wherein R7 is C1-10 alkyl group; wherein b is 0 to 4 and wherein c is 0 or 1; and wherein the first and second carbosiloxane monomer of formula (I) are same or different.

Abstract: The present disclosure provides a method for processing defect information of a product, which includes the following steps of: acquiring defect information on a current film layer and defect information on historical film layers; determining whether defect information exists at a target location of the historical film layer if defect information exists at a target location of the current film layer; if defect information exists for a corresponding location to the target location in at least one of the historical film layers, deleting the defect information detected at the target location in the current film layer; and if no defect information exists for the target location in any of the historical film layers, retaining the defect information detected at the target location in the current film layer.

Abstract: A method for extracting and isolating a lutein crystal from a vegetable oil resin containing a lutein diester, comprises: dissolving lipase into deionized water to form an enzyme solution; dissolving a lutein extract into an alcohol solvent containing the deionized water to form a uniform alcohol solution; adding the enzyme solution to the alcohol solution for performing hydrolysis, and stirring same to obtain a lutein solution; filtering and performing filtration isolation on the lutein solution to obtain a crystalline; re-dissolving the crystalline into a non-polar organic solvent, and using deionized water for washing a water-soluble impurity; recycling and cooling the organic solvent to obtain a recrystallization; and isolating and drying the recrystallization to obtain the lutein crystal. In this method, selectivity is strong, reaction time is short, no waste water is produced, process is environment-friendly and suitable for industrial production, and obtained lutein crystal is high in purity and yield.

Abstract: A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).

Abstract: A method of manufacturing a semiconductor device includes: providing bonded first and second wafers; forming a patterned insulating layer on the second substrate, the patterned insulating layer having first holes and dummy holes both exposing the second substrate; forming a protective layer, which fills a partial depth of the dummy holes and covers side surfaces of the first holes; forming through-silicon vias (TSVs); and forming a second metal layer including an interconnect metal layer and a dummy metal layer, the interconnect metal layer filling the TSVs and electrically connected to the first metal layer, the dummy metal layer filling the dummy holes. The formation of the dummy metal layer is integrated in the TSV process and is therefore done without using any additional process or adding additional cost to enable uniform pattern density (e.g., metal density) across the surface of the second wafer and enhanced CMP uniformity.

Abstract: Disclosed in the present disclosure are a semiconductor device and manufacturing method thereof. The method comprises: bonding the front surface of a top wafer to the front surface of a first wafer, and enabling the front surface of the top wafer to face upwards and the front surface of the first wafer to face downwards; bonding the front surface of a second wafer to the back surface of the first wafer to form a bonding structure, and enabling the front surface of the second wafer to face downwards; flipping the bonding structure to enable the front surface of the first wafer and the front surface of the second wafer to face upwards, and forming a pad pin in a top chip substrate.

Abstract: A metal lead, a semiconductor device and method of fabricating the same are disclosed, in which a first trench is formed simultaneously with a wiring layer trench, followed by the formation of a second trench in communication with the first trench. After that, a conductive structure is formed simultaneously with a wiring layer by filling a conductive material simultaneously in the first, second and wiring layer trenches. In this way, it is neither necessary to externally connect the conductive structure by forming an additional opening, nor to form the wiring layer by etching a deposited aluminum layer. This saves the use of two photomasks, leading to savings in production cost.

Abstract: A general and modular mechanophore platform that efficiently releases a cargo molecule via a mechanically triggered cascade reaction is described, along with methods of synthesis and use thereof. The mechanophore platform comprises a stable Diels-Alder adduct mechanophore comprising a 2-furylcarbinol derivative as its diene component, wherein the 2-furylcarbinol derivative is, in turn, pre-loaded with a covalently attached cargo molecule, and wherein the Diels-Alder adduct mechanophore is embedded into a polymer chain or polymer network, such that the mechanophore platform undergoes the retro [4+2] cycloaddition reaction under mechanical force to reveal the unstable 2-furylcarbinol derivative, which, in turn, easily decomposes under mild conditions to release its molecule cargo.

Abstract: A method, system, and device for planning a path for a forced landing of an aircraft based on image recognition are provided. The method includes: calculating an endurance distance of an aircraft based on sensor data and meteorological information; obtaining an alternative landing area by a satellite image containing contour information and a terrain image recognition model; obtaining a current satellite image of the alternative landing area and determining a landing area; and selecting a landing site by a landing site decision model and generating a path for a forced landing, such that the aircraft completes a forced landing task according to the path for the forced landing. The method, system, and device can automatically recognize image information, select a best landing site, and generate a path for a forced landing to assist a pilot in performing a forced landing task.

Abstract: A general and modular mechanophore platform that efficiently releases a cargo molecule via a mechanically triggered cascade reaction is described, along with methods of synthesis and use thereof. The mechanophore platform comprises a stable Diels-Alder adduct mechanophore comprising a 2-furylcarbinol derivative as its diene component, wherein the 2-furylcarbinol derivative is, in turn, pre-loaded with a covalently attached cargo molecule, and wherein the Diels-Alder adduct mechanophore is embedded into a polymer chain or polymer network, such that the mechanophore platform undergoes the retro [4+2] cycloaddition reaction under mechanical force to reveal the unstable2-furylcarbinol derivative, which, in turn, easily decomposes under mild conditions to release its molecule cargo.

Abstract: A bonding structure and a method for manufacturing the same. First edge trimming is performed from the bonding surface of an n-th wafer in bonding the n-th wafer and an (n?1)th wafer, and a width of the first edge trimming is Wn. As n increases, the width of the first edge trimming is gradually increased. In the trimming, a portion that is not even at the edge of the n-th wafer can be removed. The bonding surface of the n-th wafer faces the bonding surface of the (n?1)-th wafer, so as to bond the n-th wafer and the (n?1)-th wafer. Afterwards the substrate of the n-th wafer is thinned, so as to form the (n?1)-th wafer stack. There is a reduced possibility that a gap exists between the bonding interfaces of the wafers, a bonding strength between the wafers is improved, and a risk of cracking is reduced.

Abstract: A metal lead, a semiconductor device and method of fabricating the same are disclosed, in which a first trench is formed simultaneously with a wiring layer trench, followed by the formation of a second trench in communication with the first trench. After that, a conductive structure is formed simultaneously with a wiring layer by filling a conductive material simultaneously in the first, second and wiring layer trenches. In this way, it is neither necessary to externally connect the conductive structure by forming an additional opening, nor to form the wiring layer by etching a deposited aluminum layer. This saves the use of two photomasks, leading to savings in production cost.

Abstract: A bonding structure and a method for manufacturing the same. First edge trimming is performed from the bonding surface of an n-th wafer in bonding the n-th wafer and an (n?1)th wafer, and a width of the first edge trimming is Wn. As n increases, the width of the first edge trimming is gradually increased. In the trimming, a portion that is not even at the edge of the n-th wafer can be removed. The bonding surface of the n-th wafer faces the bonding surface of the (n?1)-th wafer, so as to bond the n-th wafer and the (n?1)-th wafer. Afterwards the substrate of the n-th wafer is thinned, so as to form the (n?1)-th wafer stack. There is a reduced possibility that a gap exists between the bonding interfaces of the wafers, a bonding strength between the wafers is improved, and a risk of cracking is reduced.

Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.

Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.

Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.