Patents by Inventor Tian ZENG

Tian ZENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200402945
    Abstract: A bonding structure and a method for manufacturing the same. First edge trimming is performed from the bonding surface of an n-th wafer in bonding the n-th wafer and an (n?1)th wafer, and a width of the first edge trimming is Wn. As n increases, the width of the first edge trimming is gradually increased. In the trimming, a portion that is not even at the edge of the n-th wafer can be removed. The bonding surface of the n-th wafer faces the bonding surface of the (n?1)-th wafer, so as to bond the n-th wafer and the (n?1)-th wafer. Afterwards the substrate of the n-th wafer is thinned, so as to form the (n?1)-th wafer stack. There is a reduced possibility that a gap exists between the bonding interfaces of the wafers, a bonding strength between the wafers is improved, and a risk of cracking is reduced.
    Type: Application
    Filed: September 25, 2019
    Publication date: December 24, 2020
    Applicant: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventor: Tian ZENG
  • Patent number: 10867969
    Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 15, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Patent number: 10811339
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 20, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tian Zeng
  • Patent number: 10784163
    Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Tian Zeng, Changlin Zhao
  • Publication number: 20200286861
    Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Changlin ZHAO, Tian ZENG
  • Publication number: 20200257087
    Abstract: The disclosure provides an optical imaging lens, a camera module and a mobile phone. The optical imaging lens sequentially includes: a first lens having a positive refractive power, a convex object side surface and a concave image side surface; a second lens with a negative refractive power; a third lens with a positive refractive power; a fourth lens with a negative refractive power, wherein an object side surface of the fourth lens is concave at the paraxial region, and an image side surface of the fourth lens is convex at the paraxial region; a fifth lens with a negative refractive power, an image side surface of the fifth lens being concave at the paraxial region; a sixth lens with a positive refractive power; and a seventh lens with a negative refractive power.
    Type: Application
    Filed: April 25, 2020
    Publication date: August 13, 2020
    Inventors: XUMING LIU, Haojie Zeng, Tian Zhang, Jiyong Zeng
  • Patent number: 10700042
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 30, 2020
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Changlin Zhao, Tian Zeng
  • Publication number: 20200075549
    Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 5, 2020
    Inventors: Changlin ZHAO, Tian ZENG
  • Publication number: 20200075411
    Abstract: A multi-wafer stacking structure and a fabrication method thereof are disclosed. A first dielectric layer and a second dielectric layer are bonded to each other, a first interconnection layer is electrically connected with a second metal layer and a first metal layer via a first opening; a third dielectric layer and an insulating layer are bonded to each other, and a second interconnection layer is electrically connected with a third metal layer and the first interconnection layer via a second opening. Reservation of a pressure welding lead space among wafers is not needed, a silicon substrate is omitted, multi-wafer stacking thickness is reduced while interconnection of multiple pieces of wafers is realized, and therefore, the overall thickness of the device after multi-wafer stacking and packaging is reduced, packaging density is increased, and the requirement of thinning of the semiconductor products is met.
    Type: Application
    Filed: December 28, 2018
    Publication date: March 5, 2020
    Inventors: Tian ZENG, Changlin ZHAO
  • Publication number: 20200075459
    Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
    Type: Application
    Filed: April 24, 2019
    Publication date: March 5, 2020
    Inventor: Tian Zeng