Patents by Inventor Tiancheng Gong

Tiancheng Gong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12174322
    Abstract: Provided are an F-P sensor probe, an absolute distance measurement device, and an absolute distance measurement method, which relate to the field of non-contact absolute distance measurement technologies. This structure includes a first N+1-core multimode optical fiber probe (9), an optical fiber sleeve (10), an imaging lens group (11), and a reference lens (12), wherein: the first N+1-core multimode optical fiber probe (9), the imaging lens group (11), and the reference lens (12) are sequentially fixed inside the optical fiber sleeve (10) along a direction of the F-P sensor probe toward a sample (8); and the first N+1-core multimode optical fiber probe (9) includes N first multimode optical fibers (16) and one second multimode optical fiber (17), where N?2, and the N first multimode optical fibers (16) are arranged around the second multimode optical fiber (17).
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: December 24, 2024
    Assignee: THE INSTITUTE OF OPTICS AND ELECTRONICS, THE CHINESE ACADEMY OF SCIENCES
    Inventors: Xiangang Luo, Tiancheng Gong, Chengwei Zhao, Yanqin Wang, Guiyuan Jia, Yanwu Chu, Changtao Wang
  • Publication number: 20240264285
    Abstract: Provided are an F-P sensor probe, an absolute distance measurement device, and an absolute distance measurement method, which relate to the field of non-contact absolute distance measurement technologies. This structure includes a first N+1-core multimode optical fiber probe (9), an optical fiber sleeve (10), an imaging lens group (11), and a reference lens (12), wherein: the first N+1-core multimode optical fiber probe (9), the imaging lens group (11), and the reference lens (12) are sequentially fixed inside the optical fiber sleeve (10) along a direction of the F-P sensor probe toward a sample (8); and the first N+1-core multimode optical fiber probe (9) includes N first multimode optical fibers (16) and one second multimode optical fiber (17), where N?2, and the N first multimode optical fibers (16) are arranged around the second multimode optical fiber (17).
    Type: Application
    Filed: December 5, 2022
    Publication date: August 8, 2024
    Inventors: Xiangang LUO, Tiancheng GONG, Chengwei ZHAO, Yanqin WANG, Guiyuan JIA, Yanwu CHU, Changtao WANG
  • Patent number: 12002500
    Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 4, 2024
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Qing Luo, Xiaoxin Xu, Tiancheng Gong, Ming Liu
  • Patent number: 11776607
    Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 3, 2023
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hangbing Lv, Qing Luo, Xiaoxin Xu, Tiancheng Gong, Ming Liu
  • Publication number: 20220122997
    Abstract: Disclosed is a memory, including a plurality of memory units, wherein each memory unit includes: a bulk substrate; a source electrode, a drain electrode and a channel region extending between a source region and a drain region that are located on the bulk substrate; a deep-level defect dielectric layer on the channel region; and a gate electrode on the deep-level defect dielectric layer. The memory of the present disclosure allows the memory unit to operate in the charge trapping mode and the polarization inversion mode. Therefore, the memory has functions of both DRAM and NAND, and combines the advantages of the two.
    Type: Application
    Filed: January 28, 2019
    Publication date: April 21, 2022
    Inventors: Hangbing LV, Qing LUO, Xiaoxin XU, Tiancheng GONG, Ming LIU
  • Publication number: 20220115052
    Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.
    Type: Application
    Filed: January 28, 2019
    Publication date: April 14, 2022
    Inventors: Hangbing LV, Qing LUO, Xiaoxin XU, Tiancheng GONG, Ming LIU
  • Publication number: 20220093150
    Abstract: The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.
    Type: Application
    Filed: January 28, 2019
    Publication date: March 24, 2022
    Inventors: Hangbing Lv, Qing Luo, Xiaoxin Xu, Tiancheng Gong, Ming Liu