Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.

Abstract: An apparatus and method for ensuring the reliability of a trip protection of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together. The main FPGA and the auxiliary FPGA are connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are connected to a state monitoring data output end of a protected device. The main CPU sends a processing result to the main FPGA, the auxiliary CPU sends the processing result to the auxiliary FPGA, and the auxiliary FPGA synchronizes current information with the main FPGA after receiving information sent by the auxiliary CPU. When the main FPGA receives trip information, the main FPGA comparing the consistency of current trip information obtained from the main CPU with current trip information obtained from the auxiliary FPGA.

Abstract: Disclosed by the present invention are a running method for an embedded type virtual device and a system, an embedded type device being divided into a managing process, a plurality of real-time modules and a plurality of non-real-time modules. The managing process reading a configuration file, loading real-time and non-real-time module libraries of each processor and completing initialization interaction by means of a virtual controller area network (CAN) bus and first in, first out (FIFO) communication. The managing process starting a real-time thread and serially scheduling real-time task according to a task period setting relation. The managing process starting a plurality of non-real-time threads, calling a period task of a non-real-time module and carrying out parallel communication with a plurality of debugging clients. The real-time modules exchange data with each other by means of a virtual data bus, and the real-time modules exchange data with the non-real-time modules by means of a sharing memory.

Abstract: An apparatus and method for ensuring the reliability of a protection trip of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together, wherein the main FPGA and the auxiliary FPGA are both connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are both connected to a state monitoring data output end of a protected device.

Abstract: A signal name based method for automatic signal exchange between multiple embedded CPU boards, includes: dividing CPU boards into master board and slave board, where each slave board sends signal registration information to the master board; reading an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, calculating and allocating a data bus address to which the output signal and the input signal are mapped, and sending memory addresses, data types, and bus addresses of signals to each slave board; saving these as output signal tables and input signal tables; and writing, by a signal sender, a value of an output signal into a corresponding bus address according to the output signal tables, and reading, by a receiver, a value of an input signal from a corresponding bus address according to the input signal tables.

Abstract: A signal name based method for automatic signal exchange between multiple embedded CPU boards, includes: dividing CPU boards into master board and slave board, where each slave board sends signal registration information to the master board; reading an exchange relationship between an output signal and an input signal that is represented by a connection line between signal names, calculating and allocating a data bus address to which the output signal and the input signal are mapped, and sending memory addresses, data types, and bus addresses of signals to each slave board; saving these as output signal tables and input signal tables; and writing, by a signal sender, a value of an output signal into a corresponding bus address according to the output signal tables, and reading, by a receiver, a value of an input signal from a corresponding bus address according to the input signal tables.