Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Abstract: A system and method to compress application control data, such as weights for a layer of a convolutional neural network, is disclosed. A multi-core system for executing at least one layer of the convolutional neural network includes a storage device storing a compressed weight matrix of a set of weights of the at least one layer of the convolutional network and a decompression matrix. The compressed weight matrix is formed by matrix factorization and quantization of a floating point value of each weight to a floating point format. A decompression module is operable to obtain an approximation of the weight values by decompressing the compressed weight matrix through the decompression matrix. A plurality of cores executes the at least one layer of the convolutional neural network with the approximation of weight values to produce an inference output.

Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Abstract: A system and method to compress application control data, such as weights for a layer of a convolutional neural network, is disclosed. A multi-core system for executing at least one layer of the convolutional neural network includes a storage device storing a compressed weight matrix of a set of weights of the at least one layer of the convolutional network and a decompression matrix. The compressed weight matrix is formed by matrix factorization and quantization of a floating point value of each weight to a floating point format. A decompression module is operable to obtain an approximation of the weight values by decompressing the compressed weight matrix through the decompression matrix. A plurality of cores executes the at least one layer of the convolutional neural network with the approximation of weight values to produce an inference output.

Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Abstract: A system and method to compress application control data, such as weights for a layer of a convolutional neural network, is disclosed. A multi-core system for executing at least one layer of the convolutional neural network includes a storage device storing a compressed weight matrix of a set of weights of the at least one layer of the convolutional network and a decompression matrix. The compressed weight matrix is formed by matrix factorization and quantization of a floating point value of each weight to a floating point format. A decompression module is operable to obtain an approximation of the weight values by decompressing the compressed weight matrix through the decompression matrix. A plurality of cores executes the at least one layer of the convolutional neural network with the approximation of weight values to produce an inference output.

Abstract: Systems and methods are disclosed for processing audio for an electronic device, the electronic device including an integrated speech enhanced voice trigger module that can provide an improvement over existing voice trigger modules by effectively combining together voice trigger techniques and speech enhancement techniques. In various embodiments, the integrated speech enhanced voice trigger module is configured to reduce mismatches in types and levels of noise that are encountered during both voice trigger training and runtime. This can result in a higher true positive rate (TPR), a lower false alarm (FA), and a lower impostor acceptance rate (IAR). The disclosed integrated speech enhanced voice trigger module can be used be used with an electronic device having a single microphone or a plurality of microphones.

Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.

Abstract: Disclosed are methods and systems for compressing location data of a radio for over-the-air transmission. A method includes obtaining raw latitude and raw longitude coordinates reflecting a current location of the client device, the raw latitude coordinate represented by x number of bits and the raw longitude coordinate represented by y number of bits. The raw latitude coordinate is truncated by removing n number of most significant bits from the raw latitude coordinate to create a compressed latitude coordinate. The raw longitude coordinate is truncated by removing m number of most significant bits from the raw longitude coordinate to create a compressed longitude coordinate, where m varies as a function of the value of the raw latitude coordinate. The compressed longitude and compressed latitude coordinates are then transmitted to another network device for decompression and use as an indication of the client device's absolute location.

Abstract: Disclosed are methods and systems for compressing location data of a radio for over-the-air transmission. A method includes obtaining raw latitude and raw longitude coordinates reflecting a current location of the client device, the raw latitude coordinate represented by x number of bits and the raw longitude coordinate represented by y number of bits. The raw latitude coordinate is truncated by removing n number of most significant bits from the raw latitude coordinate to create a compressed latitude coordinate. The raw longitude coordinate is truncated by removing m number of most significant bits from the raw longitude coordinate to create a compressed longitude coordinate, where m varies as a function of the value of the raw latitude coordinate. The compressed longitude and compressed latitude coordinates are then transmitted to another network device for decompression and use as an indication of the client device's absolute location.

Abstract: Disclosed are methods and systems for compressing location data of a radio for over-the-air transmission. A method includes obtaining raw latitude and raw longitude coordinates reflecting a current location of the client device, the raw latitude coordinate represented by x number of bits and the raw longitude coordinate represented by y number of bits. The raw latitude coordinate is truncated by removing n number of most significant bits from the raw latitude coordinate to create a compressed latitude coordinate. The raw longitude coordinate is truncated by removing m number of most significant bits from the raw longitude coordinate to create a compressed longitude coordinate, where m varies as a function of the value of the raw latitude coordinate. The compressed longitude and compressed latitude coordinates are then transmitted to another network device for decompression and use as an indication of the client device's absolute location.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and ?TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and ?TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and ?TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and −TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and −TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.

Abstract: A non-linear processor for use in an echo canceller is set forth. The non-linear processor includes a center clipping digital filter receiving an echo compensated signal. The non-linear processor provides a center clipped output signal having non-linear thresholds at values of +TNLP and −TNLP. The value of TNLP is dynamically dependent, at least in part, on echo return loss measurements. To limit the processor's susceptibility to corruption from double-talk conditions, the non-linear processor inhibits the dynamic setting of the TNLP value when a double-talk condition is present. Additionally, or in the alternative, the non-linear processor locks the value of the echo return loss measurement after a predetermined number of consecutive echo return loss measurements have values falling within a predetermined range of one another. Such locking further reduces the susceptibility of the non-linear processor to corruption from double-talk conditions.