Patents by Inventor TIANGE XIE

TIANGE XIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224181
    Abstract: One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 11, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tiange Xie, Li Xiang Zheng, Alex Chin Sern Ting, Zhenzhen He
  • Publication number: 20240258215
    Abstract: An example apparatus includes: a metal leadframe including a die pad in a central portion and leads spaced from the die pad. The leads include: an interior end spaced from the die pad and having a full thickness of the metal leadframe; a central portion connected to the interior end and extending away from the die pad having a partial thickness less than the full thickness; and an exterior end having the full thickness extending from the central portion. A semiconductor die is mounted to the die pad by die attach material. Wire bonds couple bond pads of the semiconductor die to the interior ends of the leads. Mold compound covers the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Mei Jiao, Huo Yun Duan, Zi Qi Wang, Tiange Xie
  • Publication number: 20230197579
    Abstract: An integrated circuit package includes a first die attach pad (DAP) having a first bottom surface, a first semiconductor die attached to the first DAP, a second DAP having a second bottom surface, wherein the first bottom surface and the second bottom surface are coplanar, and a second semiconductor die attached to the second DAP. A nonlinear DAP linking structure couples the first DAP to the second DAP, wherein the DAP linking structure does not include any direct linear connections between the first DAP and the second DAP. The nonlinear DAP linking structure is configured to deform without causing the first DAP and the second DAP to become non-coplanar. A mold compound covers the first and second DAPs, the first and second semiconductor dies, and the nonlinear DAP linking structure.
    Type: Application
    Filed: May 20, 2022
    Publication date: June 22, 2023
    Inventors: Xingfang Ma, Juan Herbsommer, Tiange Xie, Alex Chin Sern Ting
  • Publication number: 20230170282
    Abstract: A semiconductor device includes a silicon die having a first side and a second side, an adhesive layer attached to the first side of the silicon die, and a lead frame. The lead frame comprises a die attach pad having a mounting surface. The mounting surface has a smaller area than an area of the adhesive layer. The silicon die is mounted on the lead frame at the mounting surface so that edges of the silicon die and the adhesive layer overhang the die attach pad without touching the die attach pad. The semiconductor device further includes one or more leads that are spaced apart from the edges of the silicon die and the adhesive layer.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Yuntao Xu, Min Hui Ma, Tiange Xie, Rongwei Zhang
  • Publication number: 20230063278
    Abstract: One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: TIANGE XIE, LI XIANG ZHENG, ALEX CHIN SERN TING, ZHENZHEN HE