Abstract: The present disclosure provides a display panel and a display device. The display panel includes a panel body and a light-splitting component; the light-splitting component is disposed on a light-emitting side of the panel body; the light-splitting component includes a plurality of light-splitting members arranged along a first direction, and each of the light-splitting members includes a first side edge and a second side edge opposite to each other along the first direction; for any two adjacent light-splitting members, a distance between the first side edge of one of the light-splitting members and the first side edge of another one of the light-splitting members along the first direction is defined as a preset distance, X, which satisfies the following equation: X??Y, in which ? indicates angular resolution of human eye, and Y indicates an optimal viewing distance for the human eye.

Abstract: A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Abstract: Embodiments disclosed herein include immersed inductively coupled and capacitively coupled plasma excitation methods, apparatuses and processes for large area substrates. A process chamber includes a pedestal for supporting a workpiece in a processing volume, an array of inductive elements in a portion of the processing volume above the pedestal, and a chamber top or lid over the array of inductive elements.

Abstract: A light-emitting circuit includes a first transistor, a second transistor, a light-emitting element, a first switching circuit, a second switching circuit, a first capacitor, a current source, and a third switching circuit. The first switching circuit, the second switching circuit, and the third switching circuit are synchronously turned on or synchronously turned off. This not only controls the current flowing through the first switching circuit through the first capacitor, the second switching circuit and the current source to the third power line, and but also controls the current flowing through the third switching circuit, the second transistor through the first capacitor, the second switching circuit and the current source flow to the third power line. Since the current passes through the first transistor and the second transistor, the current flowing through the light-emitting element is reduced, improving adverse effects of parasitic capacitance and wire resistance to the two transistors.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode and a drain electrode. A first overlap region and a non-overlap region is defined between the gate electrode and the drain electrode. The first overlap region is adjacent to the non-overlap region. A width of a cross section of the drain electrode in the first overlap region is less than a width of a cross section of the drain electrode in the non-overlap region. The array substrate can reduce a parasitic capacitor between the gate electrode and drain electrode.

Abstract: An array substrate and a display panel are provided. The array substrate provided in the embodiments of the present disclosure includes a plurality of gate on array (GOA) units, a plurality of clock signal lines, and a plurality of communication lines. A winding area is provided between the clock signal lines and the GOA units. The communication lines are bent in the winding area. By means of the winding design, lateral capacitances of the communication lines that are on a same side are caused to be same. In this way, the problem that the lateral capacitances generated by the communication lines in different rows and surrounding traces are different is resolved.

Abstract: A storage device includes a signal input terminal, a signal output terminal, a latch, and a controller. The latch is connected between the signal input terminal and the signal output terminal, and the latch is configured to write and store data. The controller is connected between the signal input terminal and the latch. The controller includes a first transistor, a second transistor, and a control switch component, the first transistor and the second transistor are electrically connected to the latch, the control switch component is electrically connected to the first transistor and the second transistor to control the first transistor and the second transistor to be turned on or off. A leakage current of the first transistor is less than a leakage current of the second transistor, and a mobility of the second transistor is greater than a mobility of the first transistor.

Abstract: A light-emitting circuit includes a first transistor, a second transistor, a light-emitting element, a first switching circuit, a second switching circuit, a first capacitor, a current source, and a third switching circuit. The first switching circuit, the second switching circuit, and the third switching circuit are synchronously turned on or synchronously turned off. This not only controls the current flowing through the first switching circuit through the first capacitor, the second switching circuit and the current source to the third power line, and but also controls the current flowing through the third switching circuit, the second transistor through the first capacitor, the second switching circuit and the current source flow to the third power line. Since the current passes through the first transistor and the second transistor, the current flowing through the light-emitting element is reduced, improving adverse effects of parasitic capacitance and wire resistance to the two transistors.

Abstract: The present application provides a pixel structure and a display panel. The pixel structure includes pixel units, data lines, and scan lines. The pixel unit includes a main pixel region and a sub-pixel region. Each data line includes a first data line section, a second data line section, and a third data line section. Each first data line section is arranged between the two main pixel regions of two adjacent pixel units. The second data line section and the third data line section are arranged in the two sub-pixel regions of adjacent two pixel units, respectively.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode and a drain electrode. A first overlap region and a non-overlap region is defined between the gate electrode and the drain electrode. The first overlap region is adjacent to the non-overlap region. A width of a cross section of the drain electrode in the first overlap region is less than a width of a cross section of the drain electrode in the non-overlap region. The array substrate can reduce a parasitic capacitor between the gate electrode and drain electrode.

Abstract: A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Abstract: The present invention discloses an array substrate and a display device. The present invention employs a flip pixel framework of a DD+G wiring method, and a design of disposing a GOA circuit on a source electrode driver side. Because two of the data lines adjacently and parallelly enter an AA region, the gate electrode fanout wire and the two data lines are not adjacent to each other but parallelly extend in AA region, which prevents coupling between the gate electrode fanout wire and the data lines signal. The method of using the width of two pixel units to perform a layout of a GOA circuit of one level further facilitates achievement of the narrow border.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer; a carrier of the first substrate includes a plurality of carriers, a spacer layer of the second substrate includes a plurality of spacers, each carrier disposed corresponds to each spacer, wherein the carrier comprises a base and at least one sub-carrier disposed on the base. The present disclosure adopts different thickness of the carriers to form a step difference, thereby relieving surface pressure of the display panel and saving manufacturing cost.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a first substrate, a second substrate, and a liquid crystal layer; a carrier of the first substrate includes a plurality of carriers, a spacer layer of the second substrate includes a plurality of spacers, each carrier disposed corresponds to each spacer, wherein the carrier comprises a base and at least one sub-carrier disposed on the base. The present disclosure adopts different thickness of the carriers to form a step difference, thereby relieving surface pressure of the display panel and saving manufacturing cost.

Abstract: The present application provides a display panel, comprising a display area and a border area disposed at a periphery of the display area, the border area comprising: an array substrate comprising a first substrate and a gate driver on array (GOA) circuit disposed on the first substrate; a color filter substrate comprising a second substrate and a signal trace disposed on the second substrate; wherein the GOA circuit is overlapped with the signal trace. The present application also relates to a display device.

Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

Abstract: A display panel and a spliced display panel are provided. The display panel includes a GOA circuit, a GOA signal bus, and a chip-on-film area. The present invention changes a traditional way that signal outputs from both sides of the chip-on-film area to a way that signal outputs from each thin-film chip, so as to reduce signal difference in wiring of a GOA bus.

Abstract: A gate on array (GOA) device and a gate driving circuit are provided. The GOA device includes at least two GOA units. Each of the at least two GOA units includes at least one pull-down maintenance unit. The pull-down maintenance unit at least includes a first thin film transistor. The first thin film transistor includes a base substrate, a first electrode, a second electrode, and a third electrode. An electric potential of the first electrode is different from an electric potential of the second electrode. The first electrode or the second electrode is electrically connected to the third electrode.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. A pull-down maintaining module of the GOA circuit includes an eleventh transistor and a twelfth transistor to remove a residual charge of a second node and a third node to enhance a stability of the GOA circuit.

Abstract: The present application provides a display panel. The display panel includes multiple sub-pixels, multiple data lines, multiple scan lines, and multiple gate fan-out lines. Each two columns of the sub-pixels constitute a sub-pixel group, two data lines are arranged between the two columns of the sub-pixels in the sub-pixel group, and any two adjacent gate fan-out lines are spaced by at least one sub-pixel group. A width of the gate fan-out line is not less than a sum of widths of the two data lines in the sub-pixel group.