Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: The present application discloses a semi-floating gate memory device, which is a double control gate semi-floating gate memory device with a high-K/metal gate and a silicon oxide/polysilicon gate. A control gate epitaxial silicon layer, a source region and a drain region are formed by an epitaxial growth structure, separate source and drain ion implantation is not needed, the mask required for source and drain ion implantation is saved, and the fabrication cost is low. The present application further discloses a method for fabricating the semi-floating gate memory device.

Abstract: The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench.

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

Abstract: A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Abstract: The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench.

Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

Abstract: An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 ?; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

Abstract: An FDSOI device structure and its fabrication method are disclosed. The device includes a silicon substrate; a buried oxide layer on the silicon substrate; a SiGe channel on the buried oxide layer, wherein the SiGe channel has a thickness in a range of 60-100 ?; a silicon layer on the SiGe channel layer; a metal gate disposed on the silicon layer, and sidewalls attached to both sides of the metal gate; and source-drain regions disposed on the silicon layer at both sides of the metal gate, wherein the source-drain regions are built in raised SiGe layers. The invention discloses a channel forming method for the FDSOI device, the method includes making a SiGe layer and an epitaxially grown silicon layer. This channel has avoided issues such as the low stress of a silicon channel and the Ge diffusion into the gate dielectric as occurred in the conventional process, thereby improving the reliability and performance of the FDSOI device.

Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.

Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.

Abstract: A method of manufacturing a fin field effect transistor is provided. A double spacer protective layer comprising an outer spacer (the first spacer) and an inner spacer (the second spacer) is formed on both sides of the gate, and the thickness of the outer spacer can be adjusted to accurately control the distance between the source/drain ion implantation area and the channel, so as to solve the problem of the hot carrier injection effect caused by the distance being too close between the channel and the source/drain area; in addition, the outer spacers and the inner spacers can be formed by only two film deposition and etching processes without adding a photolithography mask, which can effectively prevent the contact between the gate and the source/drain, so as to substantially reduce the parasitic capacitance.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.

Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.