Abstract: The disclosure provides at compounds of Formula I, compositions comprising the same, and methods of using the same, including use in treating diseases, disorders of conditions mediated by the signaling of formyl peptide receptor 1 (FPR1).

Abstract: Disclosed is a hydraulic damper comprising a rotor (1), a stator (2) and a drive shaft (3) for driving the rotor (1), the rotor (1) and the stator (2) being mutually forming a working chamber (4) in which liquid medium is accommodated, wherein the stator (2) is provided in turn with an outlet (21), a nozzle (22), an exhaust channel (23), an ejector channel (24) and an inlet (25); the outlet (21), the exhaust channel (23) and the inlet (25) are communicated with the working chamber (4) respectively; the ejector channel (24) is in communication with the outlet (21), the exhaust channel (23) and the inlet (25) respectively; the nozzle (22) is arranged at the junction where the outlet (21) is connected with the exhaust channel (23) and the ejector channel (24); the nozzle (22) is extended along the lead-out direction of the outlet (21) to the junction where the exhaust channel (23) is connected with the ejector channel (24), and the channel width of the nozzle (22) at the extension is smaller than that of the out

Abstract: An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures.

Abstract: Disclosed is a hydraulic damper comprising a rotor (1), a stator (2) and a drive shaft (3) for driving the rotor (1), the rotor (1) and the stator (2) being mutually forming a working chamber (4) in which liquid medium is accommodated, wherein the stator (2) is provided in turn with an outlet (21), a nozzle (22), an exhaust channel (23), an ejector channel (24) and an inlet (25); the outlet (21), the exhaust channel (23) and the inlet (25) are communicated with the working chamber (4) respectively; the ejector channel (24) is in communication with the outlet (21),the exhaust channel (23) and the inlet (25) respectively; the nozzle (22) is arranged at the junction where the outlet (21) is connected with the exhaust channel (23) and the ejector channel (24); the nozzle (22) is extended along the lead-out direction of the outlet (21) to the junction where the exhaust channel (23) is connected with the ejector channel (24), and the channel width of the nozzle (22) at the extension is smaller than that of the outl

Abstract: An Analog to Digital Converter (ADC) includes an ADC core, a first switched capacitor voltage regulator, and a second switched capacitor voltage regulator. The ADC core includes a plurality of digital components that sample an incoming signal based on an ADC clock, a first voltage, and a first ground and a plurality of analog components configured to operate using a second voltage and a second ground. The first switched capacitor voltage regulator produces the first voltage and the first ground for the plurality of digital components using a supply voltage, a supply ground, and the ADC clock. The second switched capacitor voltage regulator produces the second voltage and the second ground using the supply voltage, the supply ground, and the ADC clock. Switching of the first and second switched capacitor voltage regulators is performed using complementary and non-overlapping clocks having switching frequency that is based upon the ADC clock.

Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

Abstract: A system includes a pipeline analog-to-digital converter as a first stage to process an input signal, and a successive approximation register (SAR) analog-to-digital converter as a second stage to process the input signal. The SAR analog-to-digital converter includes a power adjustment element to adjust a reference voltage of the SAR analog-to-digital converter to match a full scale voltage of the pipeline-analog-to-digital converter.

Abstract: Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fall. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

Abstract: Highly power efficient transmitter output stage designs are provided. In an embodiment, the probability density function (PDF) of an input signal is divided into a plurality of regions, and samples of the input signal are processed depending on the region of the PDF within which they fail. The PDF can be divided between an inner region corresponding to samples of the input signal that are within a predetermined amplitude range, and outer regions corresponding to samples of the input signal that are outside of the predetermined amplitude range. Samples of the input signal that fall in the inner region are processed by a class A biased amplifier and samples of the input signal that fall in the outer regions are processed by a class B biased amplifier. Output stage designs according to embodiments can be implemented as power amplifiers or power digital-to-analog converters (DACs).

Abstract: Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

Abstract: Various pipeline ADCs are disclosed that substantially compensate for interference or distortion that results from imperfections with various ADC modules of the pipeline ADCs. The pipeline ADCs include various ADC stages and various compensation stages that are coupled to the various ADC stages. The various ADC stages convert their corresponding analog inputs from an analog signal domain to a digital signal domain to provide various digital output signals and various analog residual signals to subsequent ADC stages. The various compensation stages compensate for interference or distortion that is impressed onto the various analog residual signals which results from imperfections within previous ADC stages.

Abstract: A line driver comprises a driving amplifier receiving an input of the line driver, a current sense resistor connected between the driving amplifier output and the line driver output, and a feedback amplifier sensing the voltage across the current sense resistor and providing a corresponding feedback voltage that is proportional to the output current to the driving amplifier, thereby determining an output impedance at the line driver output. Precise output impedance can be realized by using a high precision resistor as the current sense resistor, and using resistive feedback amplifiers with accurate gains as the driving and feedback amplifiers. The resistance of the current sense resistor can be substantially less than the line driver output impedance, and the driving amplifier output voltage swing can be substantially less than twice the line driver output voltage swing.

Abstract: Apparatuses, methods, and systems for effective power management distribution are provided. In an embodiment, a system for providing power to a circuit block comprises a power management unit (PMU) configured on a first substrate and an integrated circuit (IC) configured on a second substrate. The PMU includes a first regulator configured to step down an input voltage and output a first regulated voltage. The IC includes the circuit block and a second regulator configured to receive the first regulated voltage and output a second regulated voltage. The second power regulated voltage provides power to the circuit block. The first regulator is more efficient than the second regulator.

Abstract: A line driver comprises a driving amplifier receiving an input of the line driver, a current sense resistor connected between the driving amplifier output and the line driver output, and a feedback amplifier sensing the voltage across the current sense resistor and providing a corresponding feedback voltage that is proportional to the output current to the driving amplifier, thereby determining an output impedance at the line driver output. Precise output impedance can be realized by using a high precision resistor as the current sense resistor, and using resistive feedback amplifiers with accurate gains as the driving and feedback amplifiers. The resistance of the current sense resistor can be substantially less than the line driver output impedance, and the driving amplifier output voltage swing can be substantially less than twice the line driver output voltage swing.