Abstract: An ultra-low temperature and high-capacity primary lithium battery and a preparation method thereof. The primary lithium battery includes a dry cell, an electrolyte and a case. The battery is made by placement of the dry cell into the case, injection of the electrolyte, primary aging, sealing and secondary aging successively. The dry cell includes multiple unit sub-cells, and each unit sub-cell is repeated lamination of a positive plate, separator, a negative plate and another separator or lamination and winding. All unit sub-cells are enclosed such that the heat generated by the primary lithium battery during operation circulates inside the battery.

Abstract: A lithium-carbon composite material and a preparation method thereof. The method includes preparation of a micron lithium powder dispersion, adjustment of the solid content of the micron lithium powder dispersion, preparation of a lithium-carbon mixture, and preparation of the lithium-carbon composite material.

Abstract: A lithium-manganese dioxide primary battery and preparation thereof. The battery has a discharge capacity greater than 3C at ?40° C., and includes multiple positive plates, multiple negative plates, multiple ceramic separators, an electrolyte and a casing. The positive plates, the negative plates and the separators are laminated in a manner of repeated “positive plate-separator-negative plate-separator” to form a dry cell. The lithium-manganese dioxide primary battery is made by placement of the dry cell into the casing, injection of the electrolyte, primary aging, sealing and secondary aging. The positive plate and the negative plate are graphene-based manganese dioxide positive plate and lithium-carbon composite negative plate, respectively. The front and back surfaces of the positive plate are respectively provided with a positive reserved tab, and the front and back surfaces of the negative plate are respectively provided with a negative reserved tab.

Abstract: Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.

Abstract: Methods for reducing coupling noise, reducing signal skew, and saving layout area for an integrated circuit. Aspects of one method may include prioritizing a plurality of clock signals for layout on a chip. The clock signals may comprise functional and test clock signals and test clock signals, where the functional and test clock signals may not both be active at the same time. The clock signals may be routed based on the prioritization, where the priority may be based on, for example, frequency and/or slew rate of each clock signal. A route guide may also be used to take into account an amount of cross-talk reduction desired for each clock signal and/or whether a metal layer may be used may also be used in routing the clock signals. The clocks signals may also be routed so that the functional clock signals may be interlaced with the test clock signals.

Abstract: Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.