Abstract: An electromagnet for an automatic transfer switch and a corresponding automatic transfer switch. The electromagnet includes a static iron core, a coil, a magnetic yoke and a movable iron core. The static iron core is fixedly disposed on a base and at an end of the electromagnet. The coil has an annular shape and is disposed adjacent to the static iron core. The magnetic yoke is disposed between the coil and the static iron core and defines an inner space together with the static iron core and the coil. The movable iron core is partially disposed within the inner space and configured to move between a first position and a second position relative to the static iron core along a center axis of the electromagnet.

Abstract: An interlock device for a bypass device, which includes a Rack In Rack Out (RIRO) mechanism, configured to drive an Automatic Transfer Switching Equipment (ATSE) from a non-operating position to an operating position and drive the ATSE from the operating position to the non-operating position. Further, the interlock device includes a first interlock mechanism which is configured to prevent the RIRO mechanism from driving the ATSE from the non-operating position to the operating position when the first switch and the fourth switch are both switched on. The interlock device also includes a second interlock mechanism which is configured to prevent the RIRO mechanism from driving the ATSE from the non-operating position to the operating position when the second switch and the third switch are both switched on.

Abstract: The present application provides a multi-controller system and a coding method thereof, an electrical apparatus, a control device, a computer-readable storage medium, and a computer program product. The multi-controller system includes a master controller, a first slave controller and a second slave controller, the master controller being connected to the first slave controller through a first trigger signal line, and the first slave controller and the second slave controller being connected through a second trigger signal line; the master controller is configured to: send a first trigger signal to the first slave controller through the first trigger signal line, and code the first slave controller; the first slave controller is configured to: send a second trigger signal to the second slave controller through the second trigger signal line in response to receiving the first trigger signal, so that the second slave controller is able to be coded.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-? dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-? dielectric layer on the interfacial layer, and a metal film on the high-? dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-? dielectric layer.

Abstract: Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-? dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-? dielectric layer on the interfacial layer, and a metal film on the high-? dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-? dielectric layer.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.

Abstract: An interlock device for a bypass device. The bypass device is configured to switch a load between a main power supply and an auxiliary power supply and includes an Automatic Transfer Switching Equipment having a first switch coupled to the main power supply and a second switch coupled to the auxiliary power supply. The bypass device also includes a Manual Transfer Switching Equipment having a third switch coupled to the main power supply and a fourth switch coupled to the auxiliary power supply. The interlock device includes a mounting plate having a first side and a second side opposite to the first side; a first support member arranged at the first side of the mounting plate; and a first interlock assembly configured to prevent the first switch from being closed when the fourth switch is closed.

Abstract: Embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-Vt capability in the scaled space between nanosheets in advanced GAA nodes. One or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. In one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. After dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. If the work function was shifted in either P-dipole or N-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 ?, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

Abstract: This application relates to a control method, an apparatus, a device, a storage medium, and a program product for an energy storage system. The method may include: obtaining a first cluster voltage of a target battery cluster in the energy storage system; determining a second cluster voltage based on the first cluster voltage and a preset redundancy voltage, and determining an output voltage of a first regulator corresponding to the target battery cluster in the energy storage system based on a bus voltage and the second cluster voltage, where the redundancy voltage may be within a regulation range of the first regulator; and controlling the output voltage of the first regulator for voltage regulation on the target battery cluster.

Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one or more layers or surfaces of layers in the metal gate stack. The radical treatment may be performed once or multiple times during the methods described herein. The radical treatment comprises flowing one or more of nitrogen radicals (N2*) and hydrogen radicals (H*) over the surface of the metal gate stack.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.

Abstract: A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.

Abstract: Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-? metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-? metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: An energy storage system includes a first energy storage branch and a second energy storage branch connected in parallel. The first energy storage branch includes a first battery cluster. The second energy storage branch includes a second battery cluster and a DC/DC converter connected to the second battery cluster in series, with an output end of the DC/DC converter being connected to the second battery cluster. The DC/DC converter is configured to adjust an output current of the second energy storage branch to balance an output current of the first energy storage branch and the output current of the second energy storage branch.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise an integrated dipole region to meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, and a dipole region having an interfacial layer, a metal film substantially free of non-metal atoms on the interfacial layer, and a high-? dielectric layer on the metal film. In some embodiments, the dipole region of the electronic devices comprises an interfacial layer, a high-? dielectric layer on the interfacial layer, and a metal film on the high-? dielectric layer. In some embodiments, the methods comprise annealing the substrate to drive particles of metal from the metal film into one or more of the interfacial layer or the high-? dielectric layer.