Abstract: A system for clock management in an m columns×n rows array-based accelerators. Each row of the array may include a clock domain that clocks runtime clock cycles for the m processing elements. The clock domain includes a data detection and timing control circuit which is coupled to a common clock phase bus which provides a local clock source in multiple selectable phases, wherein the data detection and timing control circuit is configured to select a clock phase to clock a next clock cycle for a next concurrent data processing by the m processing elements. Each of m processing elements is coupled to access data from a first memory and a second memory and to generate respective outputs from each of the m processing elements to a corresponding m processing element of a same column in a subsequent neighboring row for the next processing in the next clock cycle.

Abstract: Systems and methods for a unified reconfigurable neural central processing unit is provided. In one aspect, a neural central processing unit is in communication with a memory, wherein the neural central processing unit is configured to transition between a binary neural network accelerator mode and a central processing unit mode, wherein, in the binary neural network accelerator mode, the memory is configured as an image memory and weight memories, wherein, in the central processing unit mode, the memory is reconfigured, from the image memory and the weight memories, to a data cache.

Abstract: A system for clock management in an m columns×n rows array-based accelerators. Each row of the array may include a clock domain that clocks runtime clock cycles for the m processing elements. The clock domain includes a data detection and timing control circuit which is coupled to a common clock phase bus which provides a local clock source in multiple selectable phases, wherein the data detection and timing control circuit is configured to select a clock phase to clock a next clock cycle for a next concurrent data processing by the m processing elements. Each of m processing elements is coupled to access data from a first memory and a second memory and to generate respective outputs from each of the m processing elements to a corresponding m processing element of a same column in a subsequent neighboring row for the next processing in the next clock cycle.

Abstract: The systems and methods describe a buck regulator, on-chip inductor and/or power management circuits. A buck regulator circuit can include a first switch and a second switch connected with a resonant switching circuit. The resonant switching circuit includes an inductor, a first capacitor and a second capacitor configured to reduce a switching power from a switching frequency of the buck regulator.

Abstract: Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.

Abstract: Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.

Abstract: Techniques pertaining to designs of integrated circuits having on-chip inductors with low common mode coupling effect are described. According to one aspect of the present invention, an integrated circuit is designed to have a first circuit operating at a first frequency and including a first inductor, and a second circuit including a second inductor and provided to process an input signal. The second circuit includes a second inductor and is provided to process an input signal.

Abstract: The systems and methods describe a buck regulator, on-chip inductor and/or power management circuits. A buck regulator circuit can include a first switch and a second switch connected with a resonant switching circuit. The resonant switching circuit includes an inductor, a first capacitor and a second capacitor configured to reduce a switching power from a switching frequency of the buck regulator.

Abstract: Schema-less databases can make data modeling and data management difficult and can detrimentally affect integration with an RDBMS. Inferring a schema from a schema-less database can improve integration by indicating a structure or organization of data in the schema-less database. A schema analyzer can infer a schema by processing data of the schema-less database to identify statistically significant data fields. The schema analyzer then creates a schema that comprises the statistically significant data fields. A data modeler can use the resulting schema along with a schema for a RDBMS to generate a unified data model. A user may submit a query based on the unified data model to obtain results from both databases. The data modeler translates the query from the unified model to be compatible with each of the schemas so that data may be written to or retrieved from each of the schema-less database and the RDBMS.

Abstract: Techniques pertaining to designs of integrated circuits having on-chip inductors with low common mode coupling effect are described. According to one aspect of the present invention, an integrated circuit is designed to have a first circuit operating at a first frequency and including a first inductor, and a second circuit including a second inductor and provided to process an input signal. The second circuit includes a second inductor and is provided to process an input signal.

Abstract: Schema-less databases can make data modeling and data management difficult and can detrimentally affect integration with an RDBMS. Inferring a schema from a schema-less database can improve integration by indicating a structure or organization of data in the schema-less database. A schema analyzer can infer a schema by processing data of the schema-less database to identify statistically significant data fields. The schema analyzer then creates a schema that comprises the statistically significant data fields. A data modeler can use the resulting schema along with a schema for a RDBMS to generate a unified data model. A user may submit a query based on the unified data model to obtain results from both databases. The data modeler translates the query from the unified model to be compatible with each of the schemas so that data may be written to or retrieved from each of the schema-less database and the RDBMS.