Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.

Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.