Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.