Abstract: A chirped illumination LIDAR system having a transmitter that may include a pulsed radiation illuminator that is followed by a beam forming optics. The transmitter may be configured to output, during each illumination period of a sub-group of illumination periods, a first plurality of radiation pulses that form a decimated chirp sequence of radiation pulses; the decimated chirp sequence is a sparse representation of a chirp signal. A receiver of the system may be configured to receive, during each reception period of a sub-group of reception periods, one or more received light pulses from one or more objects that were illuminated by the one or more radiation pulses transmitted during each illumination period.

Abstract: An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

Abstract: An analog to digital converter (ADC) receives first and second analog input signals. A charge sampling demultiplexer includes multiple capacitors that sample the first and second analog input signals, and generates multiple input samples representative of charge stored on the capacitors. A plurality of sub-ADCs each include first and second charge-to-time converters, which receive from the charge sampling demultiplexer respective first and second input sample of the first and second analog input signals and output respective first and second pulse-width-modulated (PWM) signals responsively to the respective first and second input samples. Temporal processing circuitry processes the PWM signals to generate a digital value indicative of a temporal difference between the first and second PWM signals. Output reordering circuitry receives the digital value from each of the sub-ADCs and generates a digital output indicative of a difference between the first and second analog input signals.

Abstract: An analog to digital converter (ADC) that may include an input configured to receive a first signal and a second signal; a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals; and a processing unit that is configured to receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on

Abstract: A method for multi-touch detection on a grid based capacitive sensor includes transmitting consecutively a first and then a second sequence of a Golay pair of sequences on a first driver line of a grid based capacitive sensor and transmitting the first and then the second sequence of a Golay pair of sequences on a second driver line, at a predefined delay with respect to transmission on the first driver line. Output on a receiver line of the grid based capacitive sensor is sampled and output originating from the first driver line is separated from output originating from the second driver line. The presence of an input object is detected responsive to the output as separated.

Abstract: A method for multi-touch detection on a grid based capacitive sensor includes transmitting consecutively a first and then a second sequence of a Golay pair of sequences on a first driver line of a grid based capacitive sensor and transmitting the first and then the second sequence of a Golay pair of sequences on a second driver line, at a predefined delay with respect to transmission on the first driver line. Output on a receiver line of the grid based capacitive sensor is sampled and output originating from the first driver line is separated from output originating from the second driver line. The presence of an input object is detected responsive to the output as separated.

Abstract: In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.

Abstract: A system and method according to the present invention for mapping a clocking scheme to determine robust clocking schemes in a logic circuit is disclosed. The circuit can be represented by a clocking graph, the clocking graph having at least one loop including a plurality of vertices, wherein two vertices represent each relevant signal, one for a rising edge and one for a falling edge. Additionally, a plurality of constraints of the logic circuit propagate through circuit delays.