Abstract: A LIDAR system includes a transmitter, a receiver, and a processor. The transmitter directs a sequence of illumination pulses toward a scene. The receiver including an array of photodetectors, which receive optical radiation reflected from the scene and output respective signals in response to the received optical radiation, a shutter which modulates the signals output by the photodetectors by applying a chirp shutter function, having a selected chirp period, to the signals, and a readout circuit, which samples and digitizes the modulated signals in each of a plurality of sampling windows, which span the chirp period, thereby generating a corresponding plurality of digitized output signals. The processor selects respective sampling windows for the photodetectors, and processes the digitized output signals in the selected respective sampling windows to generate a depth map of the scene.

Abstract: A LIDAR system that may include a transmitter and a receiver. The LIDAR system may include a transmitter and a receiver that may include an array of neuromorphic pixels and multiple accumulators. Each neuromorphic pixel may include multiple subpixels, an analog adder and a comparator; wherein for each reception period the analog adder is configured to generate an analog adder signal by adding detection signals from subpixels that are expected to receive at least one received light pulse during the reception period; wherein for each reception period the analog adder signal is indifferent to subpixels that are not expected to receive any received light pulses during the reception period; and wherein the comparator is configured to provide pixel output signals by comparing the analog adder signal to a threshold.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

Abstract: A device comprising a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit; wherein the readout circuit comprises a current control circuit and a comparator; wherein the current control circuit is configured to (a) charge the current control circuit to a pixel affected charge using at least a pixel affected current that is indicative of an electrical parameter of the pixel and (b) drain, based on the pixel affected charge, a current control circuit current during a comparison period; wherein the comparator is configured to compare, during the comparison period, between a pixel affected voltage and a reference signal that changes during the comparison period and to provide at least one pulse that has is indicative of a value of the pixel affected voltage.

Abstract: A LIDAR system that may include a transmitter and a receiver.

Abstract: A device that may include a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit via coupling lines that comprises an output line and a reset line; wherein the readout circuit comprises (a) a comparator that is configured to track a coupling line electrical parameter to generate a pulse that is responsive to value of the electrical parameter, and (b) a pulse width to digital converter for outputting a digital output signal that is responsive to a width of the pulse.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; delay units and a processor that is configured to generate an output digital signal that represents the input analog signal based on selected edges of the PWM pulses and delayed PWM pulses.

Abstract: A device that may include a pixel, an output conductor and a charge accelerator; wherein during a readout phase of the pixel, the pixel is configured to attempt to charge the output conductor to a pixel reset voltage and the charge accelerator is configured to perform a sampling operation and a charge operation; wherein during the sampling operation the charge accelerator is configured to sample a change in an output conductor voltage; wherein during the charge operation the charge accelerator is configured to output a charge accelerator output signal that is responsive to the change of the output conductor voltage, wherein once provided, the charge accelerator output signal accelerates a charging of the output conductor to a target voltage that is proximate to the pixel reset voltage; wherein the sampling operation and the charge operation do not overlap.

Abstract: An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; and a processor that is configured to generate an output digital signal that represents the input analog signal based on the PWM pulses.

Abstract: A device comprising a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit; wherein the readout circuit comprises a current control circuit and a comparator; wherein the current control circuit is configured to (a) charge the current control circuit to a pixel affected charge using at least a pixel affected current that is indicative of an electrical parameter of the pixel and (b) drain, based on the pixel affected charge, a current control circuit current during a comparison period; wherein the comparator is configured to compare, during the comparison period, between a pixel affected voltage and a reference signal that changes during the comparison period and to provide at least one pulse that has is indicative of a value of the pixel affected voltage.

Abstract: A device that may include a pixel and a readout circuit, wherein the pixel is coupled to the readout circuit via coupling lines that comprises an output line and a reset line; wherein the readout circuit comprises (a) a comparator that is configured to track a coupling line electrical parameter to generate a pulse that is responsive to value of the electrical parameter, and (b) a pulse width to digital converter for outputting a digital output signal that is responsive to a width of the pulse.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: A device comprising a pixel, a current source, and a readout circuit; wherein during a first readout phase of the pixel, the readout circuit is configured to sample a sampled output voltage of an output node of the pixel; and wherein an output current of the pixel is set by the current source; wherein between the first readout phase of the pixel and a second readout phase of the pixel, the pixel is configured to change the output current to provide a second output current, wherein the change of the output current is responsive to radiation sensed by a radiation sensor of the pixel during a sensing period; wherein during the second readout phase of the pixel the readout circuit is configured to sample the second output current while providing the sampled output voltage to the output node of the pixel; wherein during the first readout phase of the pixel and the second readout phase of the pixel a drain source voltage of an output transistor of the pixel is maintained constant; and wherein the output transistor

Abstract: A device comprising a pixel, a current source, and a readout circuit; wherein during a first readout phase of the pixel, the readout circuit is configured to sample a sampled output voltage of an output node of the pixel; and wherein an output current of the pixel is set by the current source; wherein between the first readout phase of the pixel and a second readout phase of the pixel, the pixel is configured to change the output current to provide a second output current, wherein the change of the output current is responsive to radiation sensed by a radiation sensor of the pixel during a sensing period; wherein during the second readout phase of the pixel the readout circuit is configured to sample the second output current while providing the sampled output voltage to the output node of the pixel; wherein during the first readout phase of the pixel and the second readout phase of the pixel a drain source voltage of an output transistor of the pixel is maintained constant; and wherein the output transistor

Abstract: A device that may include a pixel, an output conductor and a charge accelerator; wherein during a readout phase of the pixel, the pixel is configured to attempt to charge the output conductor to a pixel reset voltage and the charge accelerator is configured to perform a sampling operation and a charge operation; wherein during the sampling operation the charge accelerator is configured to sample a change in an output conductor voltage; wherein during the charge operation the charge accelerator is configured to output a charge accelerator output signal that is responsive to the change of the output conductor voltage, wherein once provided, the charge accelerator output signal accelerates a charging of the output conductor to a target voltage that is proximate to the pixel reset voltage; wherein the sampling operation and the charge operation do not overlap.

Abstract: A method and apparatus for powering up and powering down a laser diode and its driver are disclosed. The disclosed method and apparatus enable the use of deep sub-micron CMOS technology to build a laser diode driver (LDD), while ensuring the low voltage limits prescribed by such technology are not exceeded. Building an LDD with deep sub-micron CMOS technology pushes circuit integration further ahead, bringing cost of LDDs and required board circuits down.

Abstract: An in-band OTDR uses a network's communication protocols to perform OTDR testing on a link. Because the OTDR signal (probe pulse) is handled like a data signal, the time required for OTDR testing is typically about the same as the time required for other global network events, and is not considered an interruption of service to users. A network equipment includes an optical time domain reflectometry (OTDR) transmitter and receiver, each operationally connected to a link to transmit and receive, respectively, an OTDR signal. When an OTDR is to be performed, a network device operationally connected to the link actuates the OTDR transmitter to transmit the OTDR signal on the link during a determined test time based on a communications protocol of the link, during which data signals are not transmitted to the network equipment. A processing system processes the OTDR signal to provide OTDR test results.

Abstract: An in-band OTDR uses a network's communication protocols to perform OTDR testing on a link. Because the OTDR signal (probe pulse) is handled like a data signal, the time required for OTDR testing is typically about the same as the time required for other global network events, and is not considered an interruption of service to users. A network equipment includes an optical time domain reflectometry (OTDR) transmitter and receiver, each operationally connected to a link to transmit and receive, respectively, an OTDR signal. When an OTDR is to be performed, a network device operationally connected to the link actuates the OTDR transmitter to transmit the OTDR signal on the link during a determined test time based on a communications protocol of the link, during which data signals are not transmitted to the network equipment. A processing system processes the OTDR signal to provide OTDR test results.

Abstract: The present invention provides systems and methods capable of reducing power consumption in an imaging device. One imaging device includes two analog to digital converters that are separately programmable and can be in different power modes. Each analog to digital converter is capable of creating an image derived from a pixel array that has a full field of view, but lower resolution.

Abstract: An image capture device includes a focusing lens, a light sensor array having a plurality of pixels arranged in a matrix of rows and columns and a plurality of optical components. Each optical component is configured to focus light on a light-sensing portion of one of the pixels. The locations of the optical components define a grid of parallel and perpendicular lines and a line spacing of the grid varies as a function of a distance from an optical axis of the focusing lens.