Abstract: Circuitry for generating a histogram of output codes produced by an analog/digital converter (ADC) on an integrated circuit chip includes a comparator, disposed on the chip together with the ADC. A first input of the comparator is coupled to receive output codes from the ADC, while a second input is coupled to receive a sequence of target codes covering at least a portion of a range of the output codes. A pulse generator is disposed on the chip together with the ADC and the comparator, and coupled to receive the output of the comparator and, when the output is in the first state, to generate pulses for output from the chip at a pulse rate determined by a clock signal of the ADC.

Abstract: An analog-to-digital converter (ADC), including a plurality of first-level folded-differential-logic-encoders (FDLEs), coupled to receive an analog input signal and respective reference voltages and to provide respective outputs responsive to comparing a magnitude of the input signal to the respective reference voltages. The ADC has a second-level resultant FDLE, which is coupled to receive and combine the outputs of the first-level FDLEs to provide a digital value indicative of the magnitude of the input signal.

Abstract: An analog-to-digital converter, including a code generator, coupled to receive an input analog voltage and to one or more reference voltages, and adapted to generate a digital code responsive thereto, and one or more folded differential logic encoders (FDLEs) . Each of the FDLEs includes a plurality of capacitors and switching logic. The switching logic is coupled to receive the digital code and distribute a charge between the plurality of capacitors responsive to the received digital code, and to output a digital bit indicative of the input analog voltage responsive to a magnitude of a potential generated by the distributed charge on at least one of the plurality of capacitors.

Abstract: Circuitry for generating a histogram of output codes produced by an analog/digital converter (ADC) on an integrated circuit chip includes a comparator, disposed on the chip together with the ADC. A first input of the comparator is coupled to receive output codes from the ADC, while a second input is coupled to receive a sequence of target codes covering at least a portion of a range of the output codes. A pulse generator is disposed on the chip together with the ADC and the comparator, and coupled to receive the output of the comparator and, when the output is in the first state, to generate pulses for output from the chip at a pulse rate determined by a clock signal of the ADC.