Patents by Inventor Tibor Bolom
Tibor Bolom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10644099Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.Type: GrantFiled: October 24, 2018Date of Patent: May 5, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Robert V. Seidel, Thomas G. McKay, Tibor Bolom
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Publication number: 20200135845Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.Type: ApplicationFiled: October 24, 2018Publication date: April 30, 2020Applicant: GLOBALFOUNDRIES INC.Inventors: Robert V. Seidel, Thomas G. McKay, Tibor Bolom
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Patent number: 9559059Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.Type: GrantFiled: October 29, 2014Date of Patent: January 31, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
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Patent number: 9466530Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.Type: GrantFiled: October 29, 2014Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
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Publication number: 20160126190Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
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Publication number: 20160126135Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Xunyuan Zhang, Tibor Bolom, Errol Todd Ryan
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Publication number: 20150325467Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Xunyuan Zhang, Tibor Bolom, Kun Ho Ahn, Bernd Hintze, Frank Koschinsky
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Patent number: 9177858Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.Type: GrantFiled: May 8, 2014Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Xunyuan Zhang, Tibor Bolom, Kun Ho Ahn, Bernd Hintze, Frank Koschinsky
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Patent number: 9111938Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: GrantFiled: November 12, 2014Date of Patent: August 18, 2015Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., Renesas Electronics Corporation, STMICROELECTRONICS, INC.Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
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Patent number: 9059176Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: GrantFiled: April 20, 2012Date of Patent: June 16, 2015Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC., Renesas Electronics Corporation, GLOBALFOUNDRIES, INC.Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
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Publication number: 20150061135Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: ApplicationFiled: November 12, 2014Publication date: March 5, 2015Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
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Publication number: 20140138837Abstract: A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a second diffusion barrier layer. The metal seed layer is at least lightly doped. The lined trench is then filled by electroplating with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicants: STMicroelectronics, Inc., GlobalFoundries Inc, International Business Machines CorporationInventors: Chengyu Niu, Andrew Simon, Tibor Bolom
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Publication number: 20130277842Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION, STMICROELECTRONICS, INC.Inventors: Frieder Hainrich Baumann, Chao-Kun Hu, Andrew H. Simon, Tibor Bolom, Koichi Motoyama, Chengyu Charles Niu
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Patent number: 8105942Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.Type: GrantFiled: April 20, 2010Date of Patent: January 31, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jihong Choi, Tibor Bolom
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Publication number: 20110254139Abstract: An improved metal interconnect is formed with reduced metal voids and dendrites. An embodiment includes forming a mask layer on a dielectric layer, forming openings in the mask and dielectric layers, depositing a planarization layer over the mask layer and filling the openings, planarizing to remove the mask layer, removing the planarization layer from the openings, and filling the openings with metal. The planarization step prior to depositing the metal removes the etch undercut that occurs during formation of the openings and reduces the aspect ratio in the openings, thereby improving metal fill uniformity.Type: ApplicationFiled: April 20, 2010Publication date: October 20, 2011Applicant: GLOBALFOUNDRIES Inc.Inventors: Jihong Choi, Tibor Bolom
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Patent number: 7985928Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.Type: GrantFiled: August 13, 2008Date of Patent: July 26, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (“AMD”)Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
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Patent number: 7671362Abstract: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.Type: GrantFiled: December 10, 2007Date of Patent: March 2, 2010Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)Inventors: Tibor Bolom, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Paul S. McLaughlin, Sujatha Sankaran, Andrew H. Simon, Theodorus E. Standaert, James Werking
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Publication number: 20090151981Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture.Type: ApplicationFiled: August 13, 2008Publication date: June 18, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES INC. ("AMD")Inventors: Tibor Bolom, Stephan Grunow, David L. Rath, Andrew Herbert Simon
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Publication number: 20090146143Abstract: A test structure for integrated circuit (IC) device fabrication includes a plurality of test structure chains formed at various regions of an IC wafer, each of the plurality of test structure chains including one or more vias; each of the one or more vias in contact with a conductive line disposed thereabove, the conductive line being configured such that at least one dimension thereof varies from chain to chain so as to produce variations in seed layer and liner layer thickness from chain to chain for the same deposition process conditions.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC. (AMD)Inventors: Tibor Bolom, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Paul S. McLaughlin, Sujatha Sankaran, Andrew H. Simon, Theodorus E. Standaert, James Werking
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Patent number: 7446036Abstract: A microelectronic structure and a method for fabricating the microelectronic structure use a dielectric layer that is located and formed upon a first conductor layer. An aperture is located through the dielectric layer. The aperture penetrates vertically into the first conductor layer and extends laterally within the first conductor layer beneath the dielectric layer while not reaching the dielectric layer, to form an extended and winged aperture. A contiguous via and interconnect may be formed anchored into the extended and winged aperture while using a plating method, absent voids.Type: GrantFiled: December 18, 2007Date of Patent: November 4, 2008Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Tibor Bolom, Stephan Grunow, David Rath, Andrew Herbert Simon