Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

Abstract: A lead-free power semiconductor package (PSP) includes a substrate, multiple copper leads, a die, and an encapsulant. The substrate has alternating layers of copper and silicon nitride. The copper leads, which are not part of a leadframe, are connected to the substrate using active metal brazing. The die, which contains circuitry to allow the PSP to operate, is connected to the substrate using silver sintered paste. The encapsulant encases the substrate and the die with a portion of the multiple leads being outside the encapsulant.

Abstract: A substrate package arrangement may include a substrate that contains a ceramic body, a top metal layer, disposed on a top side of the ceramic body, and a bottom metal layer, disposed on a bottom side of the ceramic body, opposite the top surface. The substrate package arrangement may further include a lead structure, electrically connected to the top metal layer, and being electrically isolated from the bottom metal layer, wherein the substrate and lead structure are arranged in a discrete package, and wherein the ceramic body is formed of a high thermal conductivity material.

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

Abstract: A substrate assembly may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first direct copper bonded (DCB) surface connected to a ceramic tile. The chip is soldered onto the first DCB surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.

Abstract: A pressure contact assembly includes a power substrate, a chip, and a lead. The power substrate has a surface connected to a ceramic tile and a cavity. The chip is soldered to the surface. The lead is to be inserted into the cavity and has a top portion to connect to an external device and a bottom portion to fit into the cavity.

Abstract: A clip preform includes a die contact portion and an aligner structure. An intermediate portion connects the die contact portion to a lead contact portion in the aligner structure. The die contact portion is configured to contact a semiconductor die. The aligner structure is configured to attach the lead contact portion to a lead post. The die contact portion, the intermediate portion, and the aligner structure form a structure of a primary clip for connecting the semiconductor die to the lead post. The clip preform is severable by removing parts of the die contact portion and the intermediate portion of the clip preform to form a secondary clip for connecting the semiconductor die to the lead post. The aligner structure, a remaining part of the die contact portion, and a remaining part of the intermediate portion of the clip preform form a structure of the secondary clip.

Abstract: In a general aspect, a method can include coupling a semiconductor component to a leadframe. The leadframe can include a socket member having a first end portion and a second end portion. The socket member can further include an opening disposed between the first end portion and the second end portion. The opening of the socket member can be configured to receive a solderless pin. The method can also include encapsulating, in a molding compound, at least a portion of the leadframe and at least a portion of the semiconductor component such that the opening of the socket member is exposed through the molding compound.

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

Abstract: In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.

Abstract: Implementations of semiconductor clips may include a die attach portion coupled to a step portion, a lead attach portion directly coupled to the step portion, a first alignment feature directly coupled to a first side of the lead attach portion, and a second alignment feature directly coupled to a second side of the lead attach portion. The second side may be opposite the first side. The lead attach portion may be in a plane substantially parallel with a plane formed by the die attach portion.

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

Abstract: In a general aspect, a method can include coupling a semiconductor component to a leadframe. The leadframe can include a socket member having a first end portion and a second end portion. The socket member can further include an opening disposed between the first end portion and the second end portion. The opening of the socket member can be configured to receive a solderless pin. The method can also include encapsulating, in a molding compound, at least a portion of the leadframe and at least a portion of the semiconductor component such that the opening of the socket member is exposed through the molding compound.

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

Abstract: In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.

Abstract: A semiconductor package assembly has a leadframe that includes a socket member into which solderless pins may be inserted as interconnects to an external component. The cost of manufacturing such a leadframe is reduced without sacrificing the ability to make solderless connections with external components such as PCBs. For example, instead of using a hard material that requires two stamping tools, the leadframes with female sockets may be made using softer copper-based materials. Moreover, the width of such leadframes is significantly smaller than the width of a leadframe with the press-fit pins included. Such a reduced width may further reduce manufacturing costs.

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.