Abstract: A first communication apparatus determines a first transmission delay indicating a transmission delay of a fine granularity service in the first communication apparatus; and the first communication apparatus sends the first transmission delay to a second communication apparatus. A service bit flow sent by a sink node meets a delay compensation requirement to ensure that a network transmission delay from a source node to the sink node and a network transmission delay from the sink node to the source node in a fine granularity service network are equal or meet an expected error range, or that the network transmission delay from the source node to the sink node and the network transmission delay from the sink node to the source node are adjusted to an expected value to meet a service requirement.

Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A power conversion device includes an input conversion module, an output conversion module, a filtering module and a controlling module, which are installed on a main board. The main board includes a first edge, a second edge, a third edge and a fourth edge. The first edge and the second edge are opposed to each other. The third edge and the fourth edge are opposed to each other. A first part of the input conversion module is located near the first edge and the third edge. A second part of the input conversion module is near the first edge and the fourth edge. An airflow channel is formed between the first part and the second part. The output conversion module is near the second edge. The filtering module is near the second edge. The controlling module is arranged between the first part and the third edge.

Abstract: A power conversion device includes an input conversion module, an output conversion module, a filtering module and a controlling module, which are installed on a main board. The main board includes a first edge, a second edge, a third edge and a fourth edge. The first edge and the second edge are opposed to each other. The third edge and the fourth edge are opposed to each other. A first part of the input conversion module is located near the first edge and the third edge. A second part of the input conversion module is near the first edge and the fourth edge. An airflow channel is formed between the first part and the second part. The output conversion module is near the second edge. The filtering module is near the second edge. The controlling module is arranged between the first part and the third edge.

Abstract: A power system including power devices connected in parallel and an allocation bus is provided. Each power devices includes an allocation signal pin, a power unit and a control unit. The control unit controls a logic level of the allocation signal pin based on an operation status of the power unit. The AND logic operation performed on the logic level of the allocation signal pin of each of the power devices results in the logic level of the allocation bus. One of the power devices is set to a master mode through a first arbitration. The other power devices monitor the operation status of each other and a status of the allocation bus. Through a second arbitration, one of the power devices under a first operation status is set to a standby mode.

Abstract: An electronic apparatus includes a converting circuit and a first control circuit. The converting circuit converts an input voltage to an output voltage. The first control circuit compares a feedback signal representing the output voltage with a target voltage to generate an error voltage. When the electronic apparatus is on a starting-up status and the error voltage is not greater than a threshold voltage, the first control circuit outputs a first driving signal to drive the converting circuit according to the error voltage. When the electronic apparatus is on a starting-up status and the error voltage is greater than the threshold voltage, the first control circuit stops outputting the first driving signal. A frequency of the first driving signal is determined according to the error voltage.

Abstract: A power system including power devices connected in parallel and a wake-up bus is provided. Each power devices includes a wake-up signal pin, a power unit and a control unit. The control unit controls a logic level of the wake-up signal pin based on an operation status of the power unit. The AND logic operation performed on the logic level of the wake-up signal pin of each of the power devices results in the logic level of the wake-up bus. The control unit of each of the power devices monitors the logic level of the wake-up bus. When the logic level of the wake-up bus is at a second logic level, at least one power device under a standby mode is switched to an operation mode.

Abstract: A one-time programmable (OTP) memory device includes a memory array. The memory array includes: a data storage section for storing application data; a verification information section including at least one verification information unit, wherein each verification information unit includes a verification address region for storing verification address information associated with an address of a subject region in the data storage section, and a reference verification data region for storing one or more reference verification data, and wherein each reference verification data is calculated through reference verification calculation on the application data stored in the subject region using a predetermined verification algorithm.

Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A one-time programmable (OTP) memory device includes a memory array. The memory array includes: a data storage section for storing application data; a verification information section including at least one verification information unit, wherein each verification information unit includes a verification address region for storing verification address information associated with an address of a subject region in the data storage section, and a reference verification data region for storing one or more reference verification data, and wherein each reference verification data is calculated through reference verification calculation on the application data stored in the subject region using a predetermined verification algorithm.

Abstract: A power system including power devices connected in parallel and a wake-up bus is provided. Each power devices includes a wake-up signal pin, a power unit and a control unit. The control unit controls a logic level of the wake-up signal pin based on an operation status of the power unit. The AND logic operation performed on the logic level of the wake-up signal pin of each of the power devices results in the logic level of the wake-up bus. The control unit of each of the power devices monitors the logic level of the wake-up bus. When the logic level of the wake-up bus is at a second logic level, at least one power device under a standby mode is switched to an operation mode.

Abstract: A power system including power devices connected in parallel and an allocation bus is provided. Each power devices includes an allocation signal pin, a power unit and a control unit. The control unit controls a logic level of the allocation signal pin based on an operation status of the power unit. The AND logic operation performed on the logic level of the allocation signal pin of each of the power devices results in the logic level of the allocation bus. One of the power devices is set to a master mode through a first arbitration. The other power devices monitor the operation status of each other and a status of the allocation bus. Through a second arbitration, one of the power devices under a first operation status is set to a standby mode.

Abstract: A power supply apparatus includes a power source, power converters and an output connector. The power converters are configured for converting an input power from the power source into conversion powers. The output connector is configured for receiving the conversion powers from the power converters and outputting a parallel output power, a serial output power or separate output powers corresponding to the conversion powers from the power converters. A method of generating power by a power supply apparatus is also disclosed herein.

Abstract: An electronic apparatus includes a converting circuit and a first control circuit. The converting circuit converts an input voltage to an output voltage. The first control circuit compares a feedback signal representing the output voltage with a target voltage to generate an error voltage. When the electronic apparatus is on a starting-up status and the error voltage is not greater than a threshold voltage, the first control circuit outputs a first driving signal to drive the converting circuit according to the error voltage. When the electronic apparatus is on a starting-up status and the error voltage is greater than the threshold voltage, the first control circuit stops outputting the first driving signal. A frequency of the first driving signal is determined according to the error voltage.

Abstract: According to a method in the present invention, first whether an inter-frame difference for each pixel in predetermined first region and second region in the dynamic image exceeds a predetermined threshold is judged to determine whether the pixel is a static information point, and when, in the second region, pixels in regions not overlapping with the first region are determined as non-static information points, judgment on the inter-frame difference and the predetermined threshold is stopped; and then static characteristic information in the dynamic image is determined based on the static information points in the first region. Preferably, the inter-frame difference for each pixel in the first region may be re-judged based on an adjusted predetermined threshold, to further determine the static characteristic information in the dynamic image, so that static opaque static characteristic information or static characteristic information with arbitrary degrees of transparency in the dynamic image can be detected.

Abstract: According to a method in the present invention, first whether an inter-frame difference for each pixel in predetermined first region and second region in the dynamic image exceeds a predetermined threshold is judged to determine whether the pixel is a static information point, and when, in the second region, pixels in regions not overlapping with the first region are determined as non-static information points, judgment on the inter-frame difference and the predetermined threshold is stopped; and then static characteristic information in the dynamic image is determined based on the static information points in the first region. Preferably, the inter-frame difference for each pixel in the first region may be re-judged based on an adjusted predetermined threshold, to further determine the static characteristic information in the dynamic image, so that static opaque static characteristic information or static characteristic information with arbitrary degrees of transparency in the dynamic image can be detected.

Abstract: A power supply apparatus includes a power source, power converters and an output connector. The power converters are configured for converting an input power from the power source into conversion powers. The output connector is configured for receiving the conversion powers from the power converters and outputting a parallel output power, a serial output power or separate output powers corresponding to the conversion powers from the power converters. A method of generating power by a power supply apparatus is also disclosed herein.

Abstract: A data de-shuffler includes a buffer having a set of addressable locations for storing data and control circuitry for de-shuffling a sequence of shuffled data samples. The control circuitry stores a first data sample of the sequence of shuffled data samples at a first location in the buffer with a first address generated from an entry in a look up table and stores a second data sample at a second location in the buffer with a second address generated by incrementing from the first address by a selected incrementation value. The first and second locations in the buffer place the first and second samples in corresponding positions in an un-shuffled sequence of samples.

Abstract: Integrated circuit provides single-pass, real-time digital image encoding by digital signal processor for variable bit rate (VBR) control to improve decoded output quality. Possible peak bit rate range for multiple groups of pictures (GOP) and averaged bit rate limit encoded signal bit rate. Possible bit rate range constraint sets upper/lower range, which is pre-specified or dynamically adapted for current and future GOPs. Signal processor calculates perceptual weighting variable at macroblock level for multiple GOPs, nominal quantization parameters for multiple GOPs, quantization parameter associated at picture level, effective bit rate for each GOP, bit allocation for each picture, and total bit allocation for multiple GOPs. Variable rate signal is recordable in DVD or camcorder device.