Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices with vertical transistors. In the test device, an active area is disposed in the scribe line region. An H-type deep trench capacitor is disposed in the active area, and has parallel first and second portions and a third portion. Each of the first and second portions has a center and two ends. The third portion is disposed between the centers of the first and second portions. First to fourth conductive pads are disposed on the two ends of the first and second portions respectively. A bar-type conductive pad is disposed between the first and second portions, having a center aligned with a center of the third portion.

Abstract: A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract: A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.

Abstract: The invention provides a method for forming a crown capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. Next, a buried plate in the substrate around the bottom part of the trench is formed, followed by the formation of a lower plate in the trench without covering the sidewall of the trench. A crown-shaped capacitor dielectric layer is thus formed along the sidewall of the trench and the lower plate. This crown capacitor, having a capacitor dielectric layer with greater surface area, provides greater capacitance.

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

Abstract: A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, the deep trench capacitor is deposited in the scribe line region and has three buried layers of three doping concentrations. An isolation region is deposited in the capacitor, and a first plug, a second and a third plug are coupled to three positions of one buried layer of the three respectively. The present invention determines whether the doping concentration of buried layers within a deep trench capacitor is valid by a first resistance measured between the first plug and the second plug and a second resistance measured between the second plug and the third plug.

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.

Abstract: Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.

Abstract: A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.

Abstract: A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract: A test device and method for detecting alignment of word lines and deep trench capacitors in DRAM devices. In the test device, parallel first and second bar-type deep trenches capacitors are disposed in the scribe line region. The first and second bar-type deep trenches capacitors extend to the first and second pairs of memory cells in the memory region adjacent to the first active area respectively. The first and second bar-type deep trenches capacitors are electrically coupled to bit line contacts of the first and second pairs of memory cells respectively. First and second transistors have sources coupled to the first and second bar-type deep trenches capacitors respectively. A first bit line contact is electrically coupled to drains of the first and second transistors.