Abstract: Systems and methods for single wavelength with dual channels for control signal and Internet data transmission are disclosed. According to an aspect, a network unit may include a communications module configured to receive a single wavelength signal having first and second channels. The first channel may carry Internet data. The second channel may carry power grid control and monitoring data. Further, the network unit may include a multiplexer configured to multiplex the Internet data and the power grid control and monitoring data.

Abstract: A connector (100) includes an insulative housing (1), a first and second ground terminals (211, 212), a first differential pair (213) and a bridge (3). The first differential pair is supported by the insulative housing (1) and positioned between the first and the second ground terminals. The bridge couples the first and the second ground terminals and disposed at an inner side of the insulative housing.

Abstract: A connector (100) includes an insulative housing (1), a first and second ground terminals (211, 212), a first differential pair (213) and a bridge (3). The first differential pair is supported by the insulative housing (1) and positioned between the first and the second ground terminals. The bridge couples the first and the second ground terminals and disposed at an inner side of the insulative housing.

Abstract: A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

Abstract: A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.