Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

Abstract: An electrostatic discharge protection structure and a chip are provided. The electrostatic discharge protection structure includes: a semiconductor substrate, an N-type well, a P-type well, a first N-type doped portion, a first P-type doped portion, a second P-type doped portion and a second N-type doped portion. The N-type well and the P-type well are located in the semiconductor substrate. The first N-type doped portion and the second P-type doped portion are located in the P-type well, and the first P-type doped portion and the second N-type doped portion are located in the N-well. The first N-type doped portion has a “T” shape structure, the first P-type doped portion has a “U” shape structure, and a part of the first N-type doped portion is located in a “U” shape opening of the first P-type doped portion.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate; a gate trench located in the substrate; a gate oxide layer located on a side wall and a bottom of the gate trench; and a gate conductive layer located on a surface of the gate oxide layer, a top of the gate conductive layer being lower than a top of the gate trench. The gate oxide layer includes an ion implantation area. A bottom of the ion implantation area is higher than a bottom of the gate conductive layer and lower than the top of the gate conductive layer, and a top of the ion implantation area is higher than or flush with the top of the gate conductive layer.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a fabricating method thereof. The semiconductor structure includes: a substrate (100), and a gate oxide layer (110) on a surface of the substrate (100); a gate stack layer (120) positioned on a surface of the gate oxide layer (110); a spacer(130) at least covering a first sidewall of the gate stack layer (120); a contact structure (140) at least positioned on the surface of the substrate (100); and a dielectric layer (150) at least positioned between the contact structure (140) and a second sidewall of the gate stack layer (120). The first sidewall and the second sidewall are arranged opposite to each other, and a thickness of the dielectric layer (150) is less than a thickness of the spacer(130). A breakdown difficulty of a fuse structure may be reduced at least.

Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

Abstract: Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.

Abstract: Provided are semiconductor and a method for manufacturing semiconductor. The semiconductor structure includes: a substrate and a gate located on the substrate, a source is formed in the substrate on one side of the gate, and a drain is formed in the substrate on another side of the gate; a dielectric layer covering a surface of the gate; a contact structure passing through the dielectric layer and electrically connected to the source or the drain, the contact structure including a stack of a first contact layer and a second contact layer, and in a direction from the source to the drain, a width of the second contact layer being greater than a width of the first contact layer; and an electrical connection layer located at a top surface of the dielectric layer and in contact with part of a top surface of the second contact layer.

Abstract: The present disclosure provides a diode-triggered bidirectional silicon controlled rectifier and circuit. The silicon controlled rectifier includes: a P-type substrate; a first P well formed in the P-type substrate, a first P-type doped region and a first N-type doped region being formed in the first P well; a second P well formed in the P-type substrate, a third N-type doped region and a fourth P-type doped region being formed in the second P well; and an N well formed in the P-type substrate, a second P-type doped region, a second N-type doped region and a third P-type doped region being formed in the N well. The second N-type doped region is electrically connected with a positive electrode of a diode string, and the first P-type doped region and the fourth P-type doped region are electrically connected with a negative electrode of the diode string.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a plurality of conductive layers, at least one target conductive layer is present in the plurality of conductive layers, and a distance from the at least one target conductive layer to the conductive plug is greater than a distance from at least one adjacent layer of the target conductive layer to the conductive plug.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding position of the source region and a corresponding position of the drain region. The gate structure includes a conductive layer having an inclined side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the inclined side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitance between a gate and the source/drain region is reduced, and device characteristics are improved.

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

Abstract: A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the two contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive line and the two contacts.

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.