Abstract: An alignment apparatus for a stroke controlling mechanism having a cam shaft with a number of cams disposed around the cam shaft includes one or more circular lines and one or more sets of circular lines formed around the cam shaft. One or more longitudinal lines are formed on an outer surface of the cam shaft in a direction parallel to the longitudinal axis of the cam shaft. A check line is formed on a side surface of each cam. The cams are disposed on the cam shaft by aligning the check line of each cam with one of the longitudinal lines and by aligning each cam with one of the circular lines. A protractor is provided to measure the angles between the check line of each cam and the longitudinal line of the cam shaft.

Abstract: In a centrally controlled resource arbitration system, each of the units concurrently requesting access sends its identity code and the binary complement thereof to a central arbitration processor. The identity codes are logically combined into a first word, and the binary complements are logically combined into a second word. A subset identifier of the requesting units is then formed by combining corresponding bits of the first and second words. Unresolved values in the subset identifier are iteratively removed to eliminate a subset of the requesting units. When all but one of the requesting units have been eliminated, access to the resource is given to the remaining unit.

Abstract: Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.The pointer directs memory accessing to prevent conflicts.

Abstract: This invention describes an automatic sorter which consists of a linear array of n modules called permuters. Each permuter contains an upper-lower pair of registers, a comparison mechanism and gating arrangement to the permuters immediately above and immediately below. A sequence of N records, N being no larger than 2n, can be loaded, one at a time, into the sorter from the top during the "down mode": at the same time each of the permuters function to save the lower-ordered record in the lower register, to expel the higher ordered record to the permuter below, and to receive a record from above into the upper register.As soon as all records are loaded, the sorter enters the "up mode" of operation, in which each permuter keeps the higher ordered record in the upper register, expels the lower-ordered record through the top, and receives a record into the lower register. The uppermost permuter thus ejects one record at a time, in sorted order.

Abstract: A bubble logic array with n data inputs for performing any Boolean (or switching) logic function. Each of the data inputs comprises binary information in the form of the presence or absence of discrete bubbles. The logic function is performed by the propagation, channeling, and interaction of the bubbles themselves. The particular logic function performed by the array may be fixed by permanent connections of selective control inputs to bubble generators. Alternatively, a universal logic array may be provided by using a further 2.sup.n bubble inputs as controls to separately personalize the array. In this manner, the logic function performed by the array may be varied with each set of controls to achieve dynamically alterable logic. When the data inputs each comprise an input bubble pattern the logic array in either the fixed form or the alterable form is capable of pipelining operations, producing one meaningful output at every bit cycle.

Abstract: A text editing system is described which is comprised of single technology elements. That is, the system is comprised of dynamic shift registers which are entirely implemented with either magnetic bubble domain devices or charge coupled devices. These shift registers can be randomly accessed using write and read decoders to provide great flexibility in entry, retrieval, and restoring of data. An editing shift register is used for text editing functions, such as insertion of data, deletion of data, etc. This editing shift register performs the data manipulation functions by using techniques such as freezing of data bits and bypassing of data bits in order to change the order of the data and to close gaps which may occur in the data. The shift registers used for storage and the editing shift register are characterized in that all data manipulation functions and all accessing functions do not require a change in the sequence of the drive field used to move the data bits.