Patents by Inventor Tien-Ching Wang
Tien-Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10622077Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.Type: GrantFiled: August 31, 2017Date of Patent: April 14, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
-
Patent number: 10409674Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.Type: GrantFiled: March 29, 2016Date of Patent: September 10, 2019Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20190252035Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: arranging a plurality of first voltage levels which are used continuously for reading first data from a plurality of first memory cells according to a first wear degree of the first memory cells; decoding the first data which is read by the arranged first voltage levels; arranging a plurality of second voltage levels which are used continuously for reading second data from the first memory cells according to a second wear degree of the first memory cells, wherein the first wear degree of the first memory cells is different from the second wear degree of the first memory cells, and a voltage gap between any two neighboring voltages levels among the first voltage levels is different from a voltage gap between any two neighboring voltage levels among the second voltage levels; and decoding the second data which is read by the arranged second voltage levels.Type: ApplicationFiled: April 25, 2019Publication date: August 15, 2019Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20180374543Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.Type: ApplicationFiled: August 31, 2017Publication date: December 27, 2018Applicant: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang
-
Patent number: 10067824Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.Type: GrantFiled: December 10, 2014Date of Patent: September 4, 2018Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Yu-Cheng Hsu, Shao-Wei Yen, Tien-Ching Wang, Yu-Hsiang Lin, Kuo-Hsin Lai, Li-Chun Liang
-
Patent number: 10025660Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.Type: GrantFiled: January 28, 2016Date of Patent: July 17, 2018Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20170255511Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.Type: ApplicationFiled: March 29, 2016Publication date: September 7, 2017Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20170168893Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.Type: ApplicationFiled: January 28, 2016Publication date: June 15, 2017Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Patent number: 9639419Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.Type: GrantFiled: June 22, 2015Date of Patent: May 2, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Patent number: 9607704Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.Type: GrantFiled: April 9, 2015Date of Patent: March 28, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Patent number: 9582224Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.Type: GrantFiled: May 4, 2015Date of Patent: February 28, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Kuo-Hsin Lai, Tien-Ching Wang
-
Patent number: 9530509Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.Type: GrantFiled: June 2, 2015Date of Patent: December 27, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai, Yu-Cheng Hsu, Chi-Heng Yang
-
Patent number: 9529666Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.Type: GrantFiled: June 4, 2014Date of Patent: December 27, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Wei Lin, Shao-Wei Yen, Yu-Hsiang Lin, Tien-Ching Wang, Kuo-Hsin Lai, Siu-Tung Lam
-
Publication number: 20160350179Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first memory cells according to a first soft-decision read voltage level to obtain a first soft-decision coding unit belonging to a block code; performing a first soft-decision decoding procedure for the first soft-decision coding unit; if the first soft-decision decoding procedure fails, reading the first memory cells according to a second soft-decision read voltage level to obtain a second soft-decision coding unit belonging to the block code, where a difference value between the first soft-decision read voltage level and the second soft-decision read voltage level is related to a wear degree of the first memory cells; and performing a second soft-decision decoding procedure for the second soft-decision coding unit. Accordingly, a decoding efficiency of block codes may be improved.Type: ApplicationFiled: August 5, 2015Publication date: December 1, 2016Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20160306693Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.Type: ApplicationFiled: June 22, 2015Publication date: October 20, 2016Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20160284414Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.Type: ApplicationFiled: June 2, 2015Publication date: September 29, 2016Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai, Yu-Cheng Hsu, Chi-Heng Yang
-
Publication number: 20160266791Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.Type: ApplicationFiled: May 4, 2015Publication date: September 15, 2016Inventors: Wei Lin, Kuo-Hsin Lai, Tien-Ching Wang
-
Patent number: 9431132Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.Type: GrantFiled: June 18, 2014Date of Patent: August 30, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Li-Chun Liang, Kuo-Hsin Lai, Pei-Yu Shih, Tien-Ching Wang
-
Publication number: 20160247575Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.Type: ApplicationFiled: April 9, 2015Publication date: August 25, 2016Inventors: Wei Lin, Tien-Ching Wang, Kuo-Hsin Lai
-
Publication number: 20160098316Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.Type: ApplicationFiled: December 10, 2014Publication date: April 7, 2016Inventors: Wei Lin, Yu-Cheng Hsu, Shao-Wei Yen, Tien-Ching Wang, Yu-Hsiang Lin, Kuo-Hsin Lai, Li-Chun Liang