Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.

Abstract: A semiconductor structure includes a first die, a second die horizontally disposed adjacent to the first die, a third die disposed over the first die and the second die, and a first dielectric material surrounding the first die and the second die, wherein a portion of the first dielectric material is disposed between the first die and the second die, and the third die is disposed over the portion of the dielectric.

Abstract: A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.

Abstract: A structure and method of forming are provided. The structure includes a dielectric layer disposed on a substrate. The structure includes a cavity in the dielectric layer, and a plurality of contacts positioned in the cavity and bonded to the substrate. A component is bonded to the plurality of contacts. Underfill is disposed in the cavity between the dielectric layer and the component. A plurality of connectors is on the dielectric layer, the connectors being connected through the dielectric layer to a conductor that is at a same level of metallization as the plurality of contacts.

Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.

Abstract: Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductor over the conductive pad, a polymeric material over the semiconductor substrate and surrounding the conductor, and a seed layer between the polymeric material and the conductor. A top surface of the conductor, a top surface of the polymeric material and a top surface of the seed layer are substantially coplanar.

Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric material over the semiconductor substrate and the conductive pad; patterning the polymeric material to form an opening exposing at least a portion of the conductive pad; disposing a conductive layer over the polymeric material and the portion of the conductive pad; and forming a conductor over the portion of the conductive pad and within the opening.

Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.

Abstract: Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Abstract: A package structure has first and second dies, a molding compound, a first redistribution layer, at least one first through interlayer via (TIV), second through interlayer vias (TIVs), an electromagnetic interference shielding layer and conductive elements. The first die is molded in the molding compound. The second die is disposed on the molding compound. The first redistribution layer is located between the conductive elements and the molding compound and electrically connected to the first and second dies. The molding compound is located between the second die and the first redistribution layer. The first and second TIVs are molded in the molding compound and electrically connected to the first redistribution layer. The second TIVs are located between the first die and the first TIV. The electromagnetic interference shielding layer is in contact with the first TIV. The conductive elements are connected to the first redistribution layer.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.