Patents by Inventor Tien Dinh
Tien Dinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11937214Abstract: Method, apparatus, and computer-readable medium of wireless communication at a sidelink device include: receiving a configuration of multiple bandwidth parts (BWPs) for sidelink communication, each bandwidth part (BWP) comprising one or more sidelink resource pools; activating a BWP from the multiple BWPs configured for the sidelink communication; and transmitting or receiving sidelink communication in resources from a resource pool in the activated BWP.Type: GrantFiled: August 31, 2021Date of Patent: March 19, 2024Assignee: QUALCOMM IncorporatedInventors: Wei Yang, Seyedkianoush Hosseini, Linhai He, Hung Dinh Ly, Tien Viet Nguyen
-
Patent number: 8988967Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.Type: GrantFiled: August 13, 2012Date of Patent: March 24, 2015Assignee: Nanya Technology Corp.Inventors: Phat Truong, Tien Dinh Le
-
Publication number: 20120307570Abstract: A method is provided for relaying data to a memory array operating in synchronization with a clock signal having a first transition edge. A data strobe signal having a second transition edge corresponding to the first transition edge is provided. A first signal is provided. The data is latched into the first signal at a first time point lagged behind the first transition edge by a first time interval until a second time point in response to the first transition edge for relaying the data of the first signal to the memory array when the second transition edge appears earlier than the first transition edge.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Inventors: Phat TRUONG, Tien Dinh LE
-
Patent number: 8264907Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.Type: GrantFiled: October 14, 2009Date of Patent: September 11, 2012Assignee: Nanya Technology Corp.Inventors: Phat Truong, Tien Dinh Le
-
Publication number: 20110085392Abstract: A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal.Type: ApplicationFiled: October 14, 2009Publication date: April 14, 2011Applicant: NANYA TECHNOLOGY CORP.Inventors: Phat TRUONG, Tien Dinh LE
-
Patent number: 7568141Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.Type: GrantFiled: December 21, 2007Date of Patent: July 28, 2009Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
-
Publication number: 20080104466Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.Type: ApplicationFiled: December 21, 2007Publication date: May 1, 2008Inventors: Sankaran Menon, Luis Basto, Tien Dinh, Thomas Tomazin, Juan Revilla
-
Patent number: 7366876Abstract: In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.Type: GrantFiled: October 31, 2000Date of Patent: April 29, 2008Assignee: Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P Singh, Gregory A. Overkamp, Tien Dinh
-
Patent number: 7313739Abstract: Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.Type: GrantFiled: December 31, 2002Date of Patent: December 25, 2007Assignee: Analog Devices, Inc.Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
-
Patent number: 7168032Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).Type: GrantFiled: December 15, 2000Date of Patent: January 23, 2007Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Charles P. Roth, Ravi P. Singh, Ravi Kolagotla, Tien Dinh
-
Publication number: 20040128596Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores. A BIST (Built-In Self Test) controller supporting a “resume” mode in addition to a “pass/fail” mode may be used to compensate for timing latencies introduced by pipeline staging in an embedded memory array.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Sankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
-
Publication number: 20040073780Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.Type: ApplicationFiled: December 15, 2000Publication date: April 15, 2004Inventors: Charles P. Roth, Ravi P. Singh, Tien Dinh, Ravi Kolagotla, Marc Hoffman, Russell Rivin
-
Publication number: 20020078420Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Inventors: Charles P. Roth, Ravi P. Singh, Ravi Kolagotla, Tien Dinh